ICS95V857AGLF IDT, Integrated Device Technology Inc, ICS95V857AGLF Datasheet

IC CLK DVR PLL 1:10 48TSSOP

ICS95V857AGLF

Manufacturer Part Number
ICS95V857AGLF
Description
IC CLK DVR PLL 1:10 48TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Driver, PLLr
Datasheet

Specifications of ICS95V857AGLF

Input
Clock
Output
SSTL-2
Frequency - Max
233MHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Frequency-max
233MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1235
800-1235-5
800-1235
95V857AGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ICS95V857AGLF
Manufacturer:
ICS
Quantity:
34 327
Price:
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ICS95V857AGLFT
Manufacturer:
ICS
Quantity:
1 108
Price:
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application:
Product Description/Features:
Specifications:
Switching Characteristics:
Functionality
0674U—01/27/09
A
n (
n (
n (
n (
n (
G
G
2
2
2
2
2
V
5 .
5 .
5 .
5 .
5 .
o
o
o
o
o
N
N
D
m
m
m
m
m
V
V
V
V
V
D
D
D
)
)
)
)
)
DDR Memory Modules / Zero Delay Board Fan Out
Provides complete DDR registered DIMM solution
with ICSSSTVF16857, ICSSSTVF16859 or
ICSSSTV32852
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
PD# for power management
Spread Spectrum-tolerant inputs
Auto PD when input signal removed
Meets PC3200 Class A+ specification for DDR-I 400
support
Covers all DDRI speed grades
CYCLE - CYCLE jitter: <50ps
OUTPUT - OUTPUT skew: <40ps
Period jitter: ±30ps
P
D
H
H
L
L
H
H
X
#
N I
C
L
P
K
U
H
H
H
L
L
L
_
T
N I
<
S
2
T
0
M
H
Integrated
Circuit
Systems, Inc.
C
) z
L
(
) 1
K
H
L
H
L
H
L
_
N I
C
C
L
H
Z
Z
H
Z
L
L
K
T
C
L
H
L
Z
Z
H
L
Z
K
C
O
F
U
B
T
_
P
O
H
Z
Z
H
Z
L
L
U
U
T
T
S
T
F
B
_
O
H
Z
Z
H
Z
L
L
U
T
C
B
B
P
y
y
p
p
L
a
a
L
s s
s s
o
o
o
o
o
S
f f
f f
n
n
f f
e
e
a t
d
d
e t
o /
o /
f f
f f
Block Diagram
CLK_INC
CLK_INT
FB_INC
FB_INT
PD#
CLK_INC
CLK_INT
6.10 mm Body, 0.50 mm Pitch = TSSOP
4.40 mm Body, 0.40 mm Pitch = TVSOP
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
AGND
AVDD
GND
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
Control
Logic
48-Pin TSSOP/TVSOP
PLL
Pin Configuration
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
ICS95V857
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9

Related parts for ICS95V857AGLF

ICS95V857AGLF Summary of contents

Page 1

Integrated Circuit Systems, Inc. 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) Recommended Application: • DDR Memory Modules / Zero Delay Board Fan Out • Provides complete DDR registered DIMM solution with ICSSSTVF16857, ICSSSTVF16859 or ICSSSTV32852 Product Description/Features: • ...

Page 2

ICS95V857 A CLKT0 B CLKC1 C GND D CLKT2 E VDD F CLK_INT CLK_INC G VDD H AGND J CLKC3 K CLKT4 CLKC2 CLKT2 CLK_INT CLK_INC AVDD AGND 0674U—01/27/09 Pin Configuration ...

Page 3

Pin Descriptions ...

Page 4

ICS95V857 Absolute Maximum Ratings Supply Voltage (VDD & AVDD -0.5V to 4.6V Logic Inputs . . . . . . . . . . . . . . . ...

Page 5

Recommended Operating Condition (see note1 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage VDD Low level input voltage V IL High level ...

Page 6

ICS95V857 Timing Requirements 85°C; Supply Voltage A A VDD PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization Switching Characteristics (see note 3) PARAMETER SYMBOL Low-to high level propagation delay time ...

Page 7

V DD/2 ICS95V857 -V DD/2 NOTE: V (TT) = GND Y , FB_OUTC FB_OUTT X 0674U—01/27/09 Parameter Measurement Information (CLKC) V (CLKC) ICS95V857 GND Figure 1. IBIS Model Output Load ...

Page 8

ICS95V857 CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0674U—01/27/09 Parameter Measurement Information t ( ...

Page 9

Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0674U—01/27/09 Parameter Measurement Information t (hper_n) t (hper_n+ (jit_Hper) (jit_Hper_n) 2xf O Figure 7. Half-Period Jitter 80% Rise t ...

Page 10

ICS95V857 INDEX INDEX AREA AREA 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information XXXX y G (LF) T Designation for tape and ...

Page 11

INDEX INDEX AREA AREA 4.40 mm. Body, 0.40 mm. pitch TSSOP (16 mil) (173 mil) Ordering Information XXXX y L (LF) T Example: 95V857ALLFT 0674U—01/27/09 c SYMBOL ...

Page 12

ICS95V857 Index Area Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. Source Reference: MLF2™ ...

Page 13

A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 7.00 Bsc 4.50 Bsc 0.86/1.00 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC ...

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