ICS9LPRS525AGILF IDT, Integrated Device Technology Inc, ICS9LPRS525AGILF Datasheet
ICS9LPRS525AGILF
Specifications of ICS9LPRS525AGILF
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ICS9LPRS525AGILF Summary of contents
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CK505 for Intel Systems Recommended Application: 56-pin CK505 compatible clock, w/fully integrated Vreg and series resistors on differential outputs Output Features: • CPU differential low power push-pull pairs • SRC differential push-pull pairs • 1 ...
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ICS9LPRS525 PC MAIN CLOCK Pin Description PIN # PIN NAME TYPE 1 PCI0/CR#_A I/O 2 VDDPCI PWR 3 PCI1/CR#_B I/O 4 PCI2/TME I/O 5 PCI3/CFG0 I/O 6 PCI4/SRC5_EN I/O 7 PCI_F5/ITP_EN I/O 8 GNDPCI PWR 9 VDD48 PWR 10 USB_48MHz/FSLA ...
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ICS9LPRS525 PC MAIN CLOCK Pin Description (continued) PIN # PIN NAME TYPE 25 SRCC3_LRS/CR#_D I/O 26 VDDSRCIO PWR 27 SRCT4_LRS OUT 28 SRCC4_LRS OUT 29 CPU_STOP#/SRCC5_LRS I/O 30 PCI_STOP#/SRCT5_LRS I/O 31 VDDSRC PWR 32 SRCC6_LRS OUT 33 SRCT6_LRS OUT 34 ...
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ICS9LPRS525 PC MAIN CLOCK General Description ICS9LPRS525 is compliant Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop chipsets. ICS9LPRS525 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy ...
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ICS9LPRS525 PC MAIN CLOCK Absolute Maximum Ratings - DC Parameters PARAMETER SYMBOL Maximum Supply Voltage VDDxxx Maximum Supply Voltage VDDxxx_IO Maximum Input Voltage Minimum Input Voltage Storage Temperature Case Temperature Input ESD protection ESD prot 1 Guaranteed by design and ...
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ICS9LPRS525 PC MAIN CLOCK NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Signal is required to be monotonic in this region. 2 input leakage current does not include ...
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ICS9LPRS525 PC MAIN CLOCK Differential Clock Tolerances CPU PPM tolerance 100 Cycle to Cycle Jitter 85 Spread -0.50% Clock Periods - Differential Outputs with Spread Spectrum Disabled 1 Clock Center SSC OFF Freq. -c2c jitter MHz AbsPer Min 100.00 9.91400 ...
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ICS9LPRS525 PC MAIN CLOCK Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Pin to Pin Skew ...
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ICS9LPRS525 PC MAIN CLOCK Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge ...
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ICS9LPRS525 PC MAIN CLOCK Table 1: CPU Frequency Select Table CPU MHz B0b7 B0b6 B0b5 266. 133. 200.00 0 ...
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ICS9LPRS525 PC MAIN CLOCK Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout ...
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ICS9LPRS525 PC MAIN CLOCK PCI_STOP# Power Management SMBus OE Bit PCI_STOP# 1 Enable 0 Disable X CPU_STOP# Power Management SMBus OE Bit PCI_STOP# 1 Enable 0 Disable X CR# Power Management SMBus OE Bit CR# 1 Enable 0 Disable X ...
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ICS9LPRS525 PC MAIN CLOCK General SMBus serial interface information for the ICS9LPRS525 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the ...
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ICS9LPRS525 PC MAIN CLOCK Byte 0 FS Readback and PLL Selection Register Bit Pin Name 7 FSLC - 6 FSLB - 5 FSLA - 4 - iAMT_EN 3 Reserved 2 - SRC_Main_SEL 1 - SATA_SEL 0 - PD_Restore Byte 1 ...
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ICS9LPRS525 PC MAIN CLOCK Byte 4 Output Enable and Spread Spectrum Disable Register Bit Pin Name 7 SRC3_OE 6 SATA/SRC2_OE 5 SRC1_OE 4 SRC0/DOT96_OE 3 CPU1_OE 2 CPU0_OE 1 PLL1_SSC_ON 0 PLL3_SSC_ON Byte 5 Clock Request Enable/Configuration Register Bit Pin ...
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ICS9LPRS525 PC MAIN CLOCK Byte 8 Device ID and Output Enable Register Bit Pin Name 7 Device_ID3 6 Device_ID2 5 Device_ID1 4 Device_ID0 3 Reserved 2 Reserved 1 SE1_OE 0 SE2_OE Byte 9 Output Control Register Bit Pin Name 7 ...
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ICS9LPRS525 PC MAIN CLOCK Byte 12 Byte Count Register Bit Pin Name 7 Reserved 6 Reserved 5 BC5 4 BC4 3 BC3 2 BC2 1 BC1 0 BC0 Byte Reserved Byte 29 Slew Rate Control Bit Pin ...
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ICS9LPRS525 PC MAIN CLOCK Test Clarification Table Comments Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use ...
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ICS9LPRS525 PC MAIN CLOCK Ordering Information 9LPRS525AFLFT Example: XXXX MAIN CLOCK TM IDT SYMBOL VARIATIONS Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type F ...
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ICS9LPRS525 PC MAIN CLOCK N E1 INDEX INDEX AREA AREA Ordering Information 9LPRS525AGLFT Example: XXXX MAIN CLOCK TM IDT c SYMBOL L E VARIATIONS - ...
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ICS9LPRS525 PC MAIN CLOCK Revision History Rev. Issue Date Description 0.1 7/21/2008 Initial Release 1. Updated pinout to remove Vout reference on pin 40 0.2 08/060/08 2. Updated VDD_IO pin descriptions to show 1.05V to 3.3V operation 1. Fixed Pagination ...