IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet

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IDT82P5088BBG

Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82P5088BBG

Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
IDT82P5088BBG
Manufacturer:
IDT
Quantity:
170
Part Number:
IDT82P5088BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FEATURES
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
 2009 Integrated Device Technology, Inc.
DESCRIPTION
per port to any combination of T1, E1 or J1 ports. In receive path, an Adaptive
Equalizer is integrated to remove the distortion introduced by the cable
attenuation. The IDT82P5088 also performs clock/data recovery, AMI/
B8ZS/HDB3 line decoding and detects and reports the LOS conditions. In
transmit path, there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper,
LBOs and Jitter Attenuator for each channel. The Jitter Attenuators in trans-
mit path and receive path both can be disabled. The IDT82P5088 supports
both Single Rail and Dual Rail system interfaces. To facilitate the network
The IDT82P5088 is an eight port line intereface that can be configured
- B8ZS/HDB3/AMI line encoding/decoding
Eight channel T1/E1/J1 long haul/short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024
KHz
Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
3.3 V and 1.8 V power supply with 5 V tolerant inputs
Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703,G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR 12/13
- AT&T Pub 62411
Per channel software selectable on:
- Wave-shaping templates for short haul and long haul LBO (Line Build
- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path and transmit path)
- Single rail/dual rail system interfaces
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
Out)
Universal Octal T1/E1/J1 LIU with Inte-
grated Clock Adapter
1
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
each channel, and different types of loopbacks can be set on a per channel
basis. Four different kinds of line terminating impedance, 75Ω, 100 Ω, 110
Ω and 120 Ω are selectable on a per channel basis. The chip also provides
driver short-circuit protection and supports JTAG boundary scanning.
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
The IDT82P5088 can be used in SDH/SONET, LAN, WAN, Routers,
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
- QRSS (Quasi Random Sequence Signals) generation and detection
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
- Analog loopback, Digital loopback, Remote loopback and Inband
Per channel cable attenuation indication
Adaptive receive sensitivity
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection for line drivers
LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces
Package:
Available in 256-pin PBGA
Green package options available
with 2
with 2
error counter
loopback
15
20
-1 PRBS polynomials for E1
-1 QRSS polynomials for T1/J1
February 5, 2009
IDT82P5088
DSC-7216/-

Related parts for IDT82P5088BBG

IDT82P5088BBG Summary of contents

Page 1

FEATURES • Eight channel T1/E1/J1 long haul/short haul line interfaces • Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays • Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024 KHz • Programmable T1/E1/J1 switchability allowing one bill of ...

Page 2

IDT82P5088 FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER Figure-1 Block Diagram 2 TDO TDI TMS TCK TRST GPIO[1:0] RESET THZ A[10:0] D[7:1] D[0]/SDO CS REFR RW/WR/SDI DS/RD/SCLK MPM SPIEN INT REFB_OUT REFA_OUT CLK_SEL[2:0] ...

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IDT82P5088 1 IDT82P5088 PIN CONFIGURATIONS .......................................................................................... 9 2 PIN DESCRIPTION ..................................................................................................................... 10 3 FUNCTIONAL DESCRIPTION .................................................................................................... 17 3.1 T1/E1/J1 MODE SELECTION .......................................................................................... 17 3.2 TRANSMIT PATH ............................................................................................................. 17 3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 17 3.2.2 ENCODER .............................................................................................................. 17 3.2.3 PULSE ...

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IDT82P5088 3.5.4 INBAND LOOPBACK.............................................................................................. 33 3.5.4.1 Transmit Activate/Deactivate Loopback Code......................................... 33 3.5.4.2 Receive Activate/Deactivate Loopback Code.......................................... 33 3.5.4.3 Automatic Remote Loopback .................................................................. 33 3.6 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 34 3.6.1 DEFINITION OF LINE CODING ERROR ............................................................... 34 3.6.2 ERROR ...

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IDT82P5088 6.1 Absolute maximum Ratings .............................................................................................. 64 6.2 Recommended Operating Conditions ............................................................................... 64 6.3 D.C. Characteristics .......................................................................................................... 65 6.4 T1/J1 Line Receiver Electrical Characteristics ................................................................. 66 6.5 E1 Line Receiver Electrical Characteristics ...................................................................... 67 6.6 T1/J1 Line Transmitter Electrical Characteristics ...

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IDT82P5088 Table-1 Pin Description .............................................................................................................. 10 Table-2 Transmit Waveform Value For ....................................................................... 19 Table-3 Transmit Waveform Value For E1 120 W ..................................................................... 19 Table-4 Transmit Waveform Value For T1 0~133 ft................................................................... 19 Table-5 Transmit Waveform Value For ...

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IDT82P5088 Table-37 TIE1 MODE Mode Select Register................................................................ 44 Table-38 TJACF: Jitter Attenuator Configuration Register for Transmit Path .............................. 44 Table-39 TCF0: Transmitter Configuration Register 0 for Transmit Path..................................... 44 Table-40 TCF1: Transmitter Configuration Register 1 for Transmit ...

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IDT82P5088 Figure-1 Block Diagram ................................................................................................................. 2 Figure-2 IDT82P5088 PBGA256 Package Pin Assignment (top view) ......................................... 9 Figure-3 E1 Waveform Template Diagram .................................................................................. 17 Figure-4 E1 Pulse Template Test Circuit ..................................................................................... 17 Figure-5 DSX-1 Waveform Template .......................................................................................... 18 Figure-6 T1 Pulse ...

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IDT82P5088 1 IDT82P5088 PIN CONFIGURATIONS TTIP4 TRING4 VDDAT4 VDDAR4 B TDN8 VDDAX4 GNDA RTIP4 TD8/ C TDN7 GNDA RRING4 TDP8 D TD7/ TDN6 GNDA GNDA TDP7 E TD5/ TD6/ TDN4 TDN5 TDP5 TDP6 F TD3/ ...

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IDT82P5088 2 PIN DESCRIPTION Table-1 Pin Description Name Type Pin No. PBGA256 TTIP1 A12 TTIP2 A8 TTIP3 A7 TTIP4 A1 TTIP5 E16 TTIP6 J16 TTIP7 K16 TTIP8 T16 Output Analog TRING1 A11 TRING2 A9 TRING3 A6 TRING4 A2 TRING5 F16 ...

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IDT82P5088 Table-1 Pin Description (Continued) Name Type Pin No. PBGA256 TD1/TDP1 G2 TD2/TDP2 G4 TD3/TDP3 F2 TD4/TDP4 F4 TD5/TDP5 E2 TD6/TDP6 E4 TD7/TDP7 D2 TD8/TDP8 C2 Input TDN1 G3 TDN2 F1 TDN3 F3 TDN4 E1 TDN5 E3 TDN6 D1 TDN7 ...

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IDT82P5088 Table-1 Pin Description (Continued) Name Type Pin No. PBGA256 LOS1 R6 LOS2 N6 LOS3 T5 LOS4 P5 Output LOS5 M5 LOS6 R4 LOS7 N4 LOS8 R3 OSCI Input B13 OSCO Output C13 CLK_SEL[0] Input D15 CLK_SEL[1] C14 CLK_SEL[2] B15 ...

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IDT82P5088 Table-1 Pin Description (Continued) Name Type Pin No. PBGA256 THZ Input B16 INT Output T11 REFR Output C16 Input R11 CS A0 Input ...

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IDT82P5088 Table-1 Pin Description (Continued) Name Type Pin No. PBGA256 SCLK Input N10 SPIEN Input N11 TRST Input R13 TMS Input T14 TCK Input T15 TDI Input T13 TDO High-Z R14 VDDDIO Power F5, G5, H5, ...

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IDT82P5088 Table-1 Pin Description (Continued) Name Type Pin No. PBGA256 VDDAR[1] Power A10 VDDAR[2] C9 VDDAR[3] A5 VDDAR[4] A4 VDDAR[5] G16 VDDAR[6] H15 VDDAR[7] M15 VDDAR[8] N16 VDDAT[1] Power B12 VDDAT[2] B9 VDDAT[3] B5 VDDAT[4] A3 VDDAT[5] E15 VDDAT[6] H14 ...

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IDT82P5088 Table-1 Pin Description (Continued) Name Type Pin No. PBGA256 GNDA Ground B3, B6, B10, B11, C3, C5, C6, C7, C8, C10, D3, D4, D7, D10, F13, F15, G13, G15, J14, K13, K14, L14, L15, M14, N13, P13, P14, P15 ...

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IDT82P5088 3 FUNCTIONAL DESCRIPTION 3.1 T1/E1/J1 MODE SELECTION The IDT82P5088 can be used as an eight-channel E1 LIU or an eight- channel T1/J1 LIU application, the TEMODE bit (T1E1 mode, 20H...) should be set to ‘0’. In T1/J1 ...

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IDT82P5088 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 250 500 Time (ns) Figure-5 DSX-1 Waveform Template TTIPn IDT82P5088 TRINGn = 100 Ω ± 5% Note: R LOAD Figure-6 T1 Pulse Template Test Circuit For J1 applications, ...

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IDT82P5088 12.Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO Table-2 Transmit Waveform Value For E1 75 Ω Sample 0000000 0000000 2 0000000 0000000 3 0000000 0000000 4 0001100 0000000 5 0110000 0000000 6 0110000 ...

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IDT82P5088 Table-6 Transmit Waveform Value For T1 266~399 ft Sample 0011111 1000011 2 0110100 1000010 3 0101111 1000001 4 0101100 0000000 5 0101011 0000000 6 0101010 0000000 7 0101001 0000000 8 0101000 0000000 9 0100101 ...

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IDT82P5088 Table-10 Transmit Waveform Value For DS1 0 dB LBO Sample 0010111 1000010 2 0100111 1000001 3 0100111 0000000 4 0100110 0000000 5 0100101 0000000 6 0100101 0000000 7 0100101 0000000 8 0100100 0000000 9 ...

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IDT82P5088 3.2.4 TRANSMIT PATH LINE INTERFACE The transmit line interface consists of TTIPn pin and TRINGn pin. The impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. If T_TERM[2] is set to ...

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IDT82P5088 TJA_IS bit. When the TJA_IS bit (INTS1, 3BH...) is ‘1’, an interrupt will be reported on the INT pin if enabled by the TJA_IE bit (INTENC1, 34H...). To avoid overflowing or underflowing, the JA-Limit function can be enabled by ...

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IDT82P5088 3.3 RECEIVE PATH The receive path consists of Receive Internal Termination, Monitor Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive Equalizer, Data Slicer, CDR (Clock and Data Recovery), Jitter Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-8. 3.3.1 RECEIVE ...

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IDT82P5088 3.3.2 LINE MONITOR In both T1/J1 and E1 short haul applications, the non-intrusive monitor- ing on channels located in other chips can be performed by tapping the mon- itored channel through a high impedance bridging circuit. Refer to 10 ...

Page 26

IDT82P5088 3.3.10 G.772 NON-INTRUSIVE MONITORING In applications using only seven channels, channel 1 can be configured to monitor the data received or transmitted in any one of the remaining chan- nels. The MON[3:0] bits (MON, 05H) determine which channel and ...

Page 27

IDT82P5088 RJA_IS bit (INTS1, 3BH...). When the RJA_IS bit is ‘1’, an interrupt will be reported on the INT pin if enabled by the RJA_IE bit (INTENC1, 34H...). To avoid overflow or underflow, the JA-Limit function can be enabled by ...

Page 28

IDT82P5088 the maximum receive sensitivity) when RAISE bit (MAINT1, 2CH...) output All Ones as AIS when RAISE bit (MAINT1, 2CH...) this case RCLKn output is replaced by MCLK. Table-19 LOS Declare and Clear Criteria ...

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IDT82P5088 Table-20 LOS Declare and Clear Criteria for Long Haul Mode Control bit TEMODE LAC LOS[4:0] 00000 00001 … 0 T1.231 10001 … 10101 10110-11111 00000 - … 00110 1=T1/J1 I.431 00111 … 01101 1 01110 … - 10001 … ...

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IDT82P5088 Table-21 AIS Condition ITU G.775 for E1 (LAC bit is set to ‘0’ by default) AIS Less than 3 zeros contained in each of two consecutive 512-bit streams are received detected AIS 3 or more zeros contained in each ...

Page 31

IDT82P5088 3.5 LOOPBACK To facilitate testing and diagnosis, the IDT82P5088 provides four dif- ferent loopback configurations: Analog Loopback, Digital Loopback, Remote Loopback and Inband Loopback. 3.5.1 ANALOG LOOPBACK When the ALP bit (MAINT0, 2BH...) is set to ‘1’, the corresponding ...

Page 32

IDT82P5088 LOS/AIS LOSn Detector RCLKn B8ZS/ RDn/RDPn HDB3/AMI CVn/RDNn Decoder Remote Loopback B8ZS/ TCLKn TDn/TDPn HDB3/AMI Encoder TDNn FUNCTIONAL DESCRIPTION UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER Clock and Jitter Data Data Attenuator Slicer Recovery Waveform Jitter Attenuator Shaper/LBO ...

Page 33

IDT82P5088 3.5.4 INBAND LOOPBACK When PATT[1:0] bits (MAINT1, 2CH...) are set to ‘11’, the correspond- ing channel is configured in Inband Loopback mode. In this mode, an acti- vate/Deactivate Loopback Code is generated repeatedly in transmit direction per ANSI T1. ...

Page 34

IDT82P5088 3.6 ERROR DETECTION/COUNTING AND INSERTION 3.6.1 DEFINITION OF LINE CODING ERROR The following line encoding errors can be detected and counted by the IDT82P5088: • Received Bipolar Violation (BPV) Error: In AMI coding, when two consecutive pulses of the ...

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IDT82P5088 • Manual Report Mode In Manual Report Mode, the internal Error Counter starts to count the received errors when the CNT_MD bit (MAINT6, 31H...) is set to ‘0’. When there is a ‘0’ to ‘1’ transition on the CNT_STOP ...

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IDT82P5088 3.8 CLOCK GENERATOR AND TCLK 3.8.1 CLOCK GENERATOR OSCO Crystal OSCI Clock Generator Oscillator CLK_SEL[2:0] Figure-19 Clock Generator The OSCI pin is connected to an external Crystal Oscillator mode E1 Rate of Transmit System interface, this clock ...

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IDT82P5088 3.9 MICROPROCESSOR INTERFACE The microprocessor interface provides access to read and write the registers in the device. The interface consists of Serial Peripheral Inter- face (SPI) and parallel microprocessor interface. 3.9.1 SPI Mode Pull the SPIEN pin to high, ...

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IDT82P5088 3.10 INTERRUPT HANDLING An active level on the INT pin represents an interrupt of the IDT82P5088. The INT_CH[7:0] bits (INTCH, 09H) should be read to identify which chan- nel(s) generate the interrupt. The interrupt event is captured by the ...

Page 39

IDT82P5088 3.11 GENERAL PURPOSE I/O The IDT82P5088 provides two general purpose digital I/O pins: GPIO1, GPIO0. These two pins can be considered as digital Input or Output port by the DIR1 bit (GPIO, 06H) and DIR0 bit (GPIO, 06H) respectively. ...

Page 40

IDT82P5088 4 PROGRAMMING INFORMATION 4.1 REGISTER LIST AND MAP The IDT82P5088 registers can be divided into Global Registers and Local Registers. The operation on the Global Registers affects all the eight channels while the operation on Local Registers only affects ...

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IDT82P5088 Table-28 Per Channel Register List and Map Address (Hex) Register R/W CH1-CH8 X20* T1E1 mode Transmit Path Control Registers X21 TJACF R/W X22 TCF0 R/W X23 TCF1 R/W X24 TCF2 R/W X25 TCF3 R/W X26 TCF4 R/W Receive Path ...

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IDT82P5088 4.3 REGISTER DESCRIPTION 4.3.1 GLOBAL REGISTERS Table-29 ID: Chip Revision Register (R, Address = 02H) Symbol Bit Default ID[7:0] 7-0 01H Table-30 RST: Reset Register (W, Address = 04H) Symbol Bit Default RST[7:0] 7-0 01H Table-31 MON: G.772 Monitor ...

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IDT82P5088 Table-32 GPIO: General Purpose IO Pin Definition Register (Continued) (R/W, Address = 06H) Symbol Bit Default LEVEL0 2 - DIR1 1 1 DIR0 0 1 Table-33 REFOUT: Reference clock output select Register (R/W, Address = 07H) Symbol Bit Default ...

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IDT82P5088 Table-36 TIMER INTS: Timer Interrupt Status Register (bit TMOV_IS is reset after writing a 1 into this bit position) Symbol Bit Default - 7-1 000000 TMOVIS 0 0 4.3.2 PER CHANNEL CONTROL REGISTERS Table-37 TIE1 MODE ...

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IDT82P5088 Table-39 TCF0: Transmitter Configuration Register 0 for Transmit Path (Continued) (R/W, Address = X22H) Symbol Bit Default T_OFF 4 0 TD_INV 3 0 TCLK_SEL 2 0 T_MD[1:0] 1-0 00 Table-40 TCF1: Transmitter Configuration Register 1 for Transmit Path (R/W, ...

Page 46

IDT82P5088 Table-41 TCF2: Transmitter Configuration Register 2 for Transmit Path (R/W, Address = X24H) Symbol Bit Default - 7-6 00 SCAL[5:0] 5-0 100001 Table-42 TCF3: Transmitter Configuration Register 3 for Transmit Path (R/W, Address = X25H) Symbol Bit Default DONE ...

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IDT82P5088 4.3.4 RECEIVE PATH CONTROL REGISTERS Table-44 RJACF: Jitter Attenuator Configuration Register for Receive Path (R/W, Address = X27H) Symbol Bit Default - 7-6 00 RJITT_TEST 5 0 RJA_LIMIT 4 1 RJA_E 3 00 RJA_DP[1:0] 2-1 00 RJA_BW 0 0 ...

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IDT82P5088 Table-46 RCF1: Receiver Configuration Register 1 for Receive Path (R/W, Address = X29H) Symbol Bit Default - 7 0 EQ_ON 6 0 FIXG 5 0 LOS[4:0] 4-0 10101 PROGRAMMING INFORMATION UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER Reserved ...

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IDT82P5088 Table-47 RCF2: Receiver Configuration Register 2 for Receive Path (R/W, Address = X2AH) Symbol Bit Default - 7-6 00 SLICE[1:0] 5-4 01 UPDW[1:0] 3-2 10 MG[1:0] 1-0 00 4.3.5 NETWORK DIAGNOSTICS CONTROL REGISTERS Table-48 MAINT0: Maintenance Function Control Register ...

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IDT82P5088 Table-49 MAINT1: Maintenance Function Control Register 1 (Continued) (R/W, Address = X2CH) Symbol Bit Default PATT_CLK 4 0 PRBS_INV 3 0 LAC 2 0 RAISE 1 0 ATAO 0 0 Table-50 MAINT2: Maintenance Function Control Register 2 (R/W, Address ...

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IDT82P5088 Table-52 MAINT4: Maintenance Function Control Register 4 (R/W, Address = X2FH) Symbol Bit Default RNLPA[7:0] 7-0 (000)00001 Defines the user-programmable receive Inband Loopback activate code. The default selection is 00001. Table-53 MAINT5: Maintenance Function Control Register 5 (R/W, Address ...

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IDT82P5088 4.3.6 TRANSMIT AND RECEIVE TERMINATION REGISTER Table-55 TERM: Transmit and Receive Termination Configuration Register (R/W, Address = X32H) Symbol Bit Default - 7-6 00 T_TERM[2:0] 5-3 000 R_TERM[2:0] 2-0 000 4.3.7 INTERRUPT CONTROL REGISTERS Table-56 INTENC0: Interrupt Mask Register ...

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IDT82P5088 Table-57 INTENC1: Interrupt Mask Register 1 (R/W, Address = X34H) Symbol Bit Default - 7 0 DAC_IE 6 0 TJA_IE 5 0 RJA_IE 4 0 ERR_IE 3 0 EXZ_IE 2 0 CV_IE 1 0 CNT_IE 0 0 PROGRAMMING INFORMATION ...

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IDT82P5088 Table-58 INTES: Interrupt Trigger Edges Select Register (R/W, Address = X35H) Symbol Bit Default - 7 0 NLPA_IES 6 0 NLPD_IES 5 0 PRBS_IES 4 0 TCLK_IES 3 0 DF_IES 2 0 AIS_IES 1 0 LOS_IES 0 0 PROGRAMMING ...

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IDT82P5088 4.3.8 LINE STATUS REGISTERS Table-59 STAT0: Line Status Register 0 (real time status monitor) (R, Address = X36H) Symbol Bit Default ARLP_S 7 0 NLPA_S 6 0 NLPD_S 5 0 PRBS_S 4 0 TCLK_LOS 3 0 PROGRAMMING INFORMATION UNIVERSAL ...

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IDT82P5088 Table-59 STAT0: Line Status Register 0 (real time status monitor) (Continued) (R, Address = X36H) Symbol Bit Default DF_S 2 0 AIS_S 1 0 LOS_S 0 0 PROGRAMMING INFORMATION UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER Line driver ...

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IDT82P5088 Table-60 STAT1: Line Status Register 1 (real time status monitor) (R, Address = X37H) Symbol Bit Default - 7 LATT[4:0] 4-0 00000 Table-61 TJITT: Jitter Measure Value Indicate Register (Transmit Path) (R/W, Address = X38H) ...

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IDT82P5088 4.3.9 INTERRUPT STATUS REGISTERS Table-63 INTS0: Interrupt Status Register 0 (This register is cleared if a ’1’ is written to it.) (R/W, Address = X3AH) Symbol Bit Default - 7 0 NLPA_IS 6 0 NLPD_IS 5 0 PRBS_IS 4 ...

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IDT82P5088 Table-64 INTS1: Interrupt Status Register 1 (This register is cleared if a ’1’ is written to it.) (R/W, Address = X3BH) Symbol Bit Default - 7 0 DAC_IS 6 0 TJA_IS 5 0 RJA_IS 4 0 ERR_IS 3 0 ...

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IDT82P5088 5 IEEE STD 1149.1 JTAG TEST ACCESS PORT The IDT82P5088 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction regis- ters plus a Test Access Port ...

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IDT82P5088 5.1 JTAG INSTRUCTIONS AND INSTRUCTION REG- ISTER The IR (Instruction Register) with instruction decode block is used to select the test to be executed or the data register to be accessed or both. The instructions are shifted in LSB ...

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IDT82P5088 5.2.4 TEST ACCESS PORT CONTROLLER The TAP controller is a 16-state synchronous state machine. shows its state diagram following the description of each state. Note that the figure contains two main branches to access either the data or instruc- ...

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IDT82P5088 Table-70 TAP Controller State Description (Continued) STATE Exit1-IR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the ...

Page 64

IDT82P5088 6 TEST SPECIFICATIONS 6.1 Absolute maximum Ratings Storage Temperature Voltage on VDDAR/VDDAT/VDDAX/VDDAB/VDDAP w.r.t. GND Voltage on VDDDIO w.r.t. GND Voltage on VDDDC w.r.t. GND Voltage on Any Input Digital Pin Voltage on Any Input Analog Pin ESD Performance (HBM) ...

Page 65

IDT82P5088 6.3 D.C. Characteristics @ TA = -40 to +85 °C, VDDDIO = 3 0.3 V, VDDDC = 1.8 + 10% Paramete r VOL Output Low Voltage VOH Output High Voltage VT+ Schmitt Trigger Input Low to High ...

Page 66

IDT82P5088 6.4 T1/J1 Line Receiver Electrical Characteristics Parameter Receiver Sensitivity Short haul with cable loss @ 772 kHz: Long haul with cable loss @ 772 kHz: Analog LOS level Short haul: Long haul: Allowable consecutive zeros before LOS T1.231 - ...

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IDT82P5088 6.5 E1 Line Receiver Electrical Characteristics Parameter Receiver Sensitivity Short haul with cable loss @ 1024 kHz: Long haul with cable loss @ 1024 kHz: Analog LOS level Short haul: Long haul: Allowable consecutive zeros before LOS G.775: I.431 ...

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IDT82P5088 Parameter Transmit Return Loss 39 KHz - 77 KHz: 77 KHz - 1.544 MHz: 1.544 MHz - 2.316 MHz: Intrinsic Transmit Jitter (TSCK is jitter free KHz: 8 KHz - 40 KHz ...

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IDT82P5088 6.8 Transmitter and Receiver Timing Characteristics Symbol Parameter OSCI frequency E1: T1/J1: MCLK tolerance MCLK duty cycle Transmit path TCLK frequency E1: T1/J1: TCLK tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data Hold Time Delay ...

Page 70

IDT82P5088 TCLKn TDn/TDPn TDNn RCLKn RDPn/RDn (RCLK_SEL = 0) RDNn/CVn RDPn/RDn (RCLK_SEL = 1) RDNn/CVn 6.9 Jitter Tolerance 6.9.1 T1/J1 Mode Jitter Tolerance 300 Hz 10 KHz - 100 KHz TEST SPECIFICATIONS UNIVERSAL OCTAL T1/E1/J1 ...

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IDT82P5088 Figure-27 T1/J1 Jitter Tolerance Performance Requirement 6.9.2 E1 Mode Jitter Tolerance 2.4 KHz 18 KHz - 100 KHz TEST SPECIFICATIONS UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER Min. Typ. Max 37 1.5 0.2 ...

Page 72

IDT82P5088 Figure-28 E1 Jitter Tolerance Performance Requirement TEST SPECIFICATIONS UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER 72 February 5, 2009 ...

Page 73

IDT82P5088 6.10 Jitter Transfer Parameter Jitter Attenuator Latency Delay 32-bit FIFO: 64-bit FIFO: 128-bit FIFO: Input jitter tolerance before FIFO overflow or underflow 32-bit FIFO: 64-bit FIFO: 128-bit FIFO: 6.10.1 T1/J1 Mode T1/J1 Jitter Transfer performance is required by AT&T ...

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IDT82P5088 Figure-29 T1/J1 Jitter Transfer Performance Requirement (AT&T62411 / GR-253-CORE / TR-TSY-000009) 6.10.2 E1 Mode E1 Jitter Transfer performance is required by G.736. Parameter @ 400 Hz @ 100 kHz TEST SPECIFICATIONS UNIVERSAL OCTAL ...

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IDT82P5088 Figure-30 E1 Jitter Transfer Performance Requirement (G.736) Table-71 JTAG Timing Characteristics Symbol t1 TCK Period t2 TMS to TCK Setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 TCK ...

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IDT82P5088 TCK TMS TDI TDO TEST SPECIFICATIONS UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER Figure-31 JTAG Interface Timing 76 February 5, 2009 ...

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IDT82P5088 7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS 7.1 Motorola Non-Multiplexed Mode 7.1.1 Read Cycle Specification Symbol tRC Read Cycle Time tDW Valid DS Width tRWV Delay from DS to Valid Read Signal tRWH Hold Time tAV Delay from ...

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IDT82P5088 Symbol tAH Address to DS Hold Time tDV Delay from DS to valid write data tDHW Write Data to DS Hold Time tRecovery Recovery Time from Write Cycle DS+CS RW A[x:0] Write D[7:0] Figure-33 Motorola Non-Multiplexed Mode Write Cycle ...

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IDT82P5088 CS+RD A[x:0] READ D[7:0] Note: The WR pin should be tied to high. 7.2.2 Write Cycle Specification Symbol tWC Write Cycle Time tWRW Valid WR width tAV Delay from WR to Valid Address tAH Address to WR Hold Time ...

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IDT82P5088 7.3 SPI Mode The maximum SPI data transfer clock is 2 MHz. Symbol CSH t CSS t CSD t CLD t CLH t CLL t DIS t DIH SCLK SDI High ...

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IDT82P5088 ORDERING INFORMATION XXXXXXX XX Device Type Package DATASHEET DOCUMENT HISTORY CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER X Process/Temperature Range BLANK BB 82P5088 for SALES: 1-800-345-7015 or ...

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