IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 31

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IDT82P5088BBG

Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82P5088BBG

Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-

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3.5
ferent loopback configurations: Analog Loopback, Digital Loopback,
Remote Loopback and Inband Loopback.
3.5.1
nel is configured in Analog Loopback mode. In this mode, the transmit sig-
nals are looped back to the Receiver Internal Termination in the receive
path then output from RCLKn, RDn, RDPn/RDNn. The all-ones pattern can
be generated during analog loopback. At the same time, the transmit sig-
nals are still output to TTIPn/TRINGn in transmit direction.
the process. The THZ bit (TCF1, 23H...) shall be set to ‘0’ in Analog Loop-
back mode.
3.5.2
nel is configured in Digital Loopback mode. In this mode, the transmit sig-
FUNCTIONAL DESCRIPTION
IDT82P5088
CVn/RDNn
To facilitate testing and diagnosis, the IDT82P5088 provides four dif-
When the ALP bit (MAINT0, 2BH...) is set to ‘1’, the corresponding chan-
When the DLP bit (MAINT0, 2BH...) is set to ‘1’, the corresponding chan-
RDn/RDPn
TDn/TDPn
RCLKn
TCLKn
CVn/RDNn
RDn/RDPn
TDn/TDPn
TDNn
LOSn
LOOPBACK
ANALOG LOOPBACK
DIGITAL LOOPBACK
RCLKn
TCLKn
LOSn
TDNn
LOS/AIS
HDB3/AMI
HDB3/AMI
Detector
Decoder
Encoder
B8ZS/
B8ZS/
LOS/AIS
HDB3/AMI
Detector
HDB3/AMI
Decoder
Encoder
B8ZS/
B8ZS/
Attenuator
Attenuator
Jitter
Jitter
Attenuator
Attenuator
Jitter
Jitter
Loopback
Digital
Figure-14
Figure-14 Analog Loopback
Figure-15 Digital Loopback
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
Clock and
Recovery
Shaper/LBO
shows
Waveform
Data
Clock and
Recovery
Shaper/LBO
Waveform
Data
31
nals are looped back to the jitter attenuator (if enabled) and decoder in
receive path, then output from RCLKn, RDn, RDPn/RDNn. At the same
time, the transmit signals are still output to TTIPn/TRINGn in transmit direc-
tion.
sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will
overwrite the transmit signals. In this case, either TCLKn or MCLK can be
used as the reference clock for internal patterns transmission.
3.5.3
nel is configured in Remote Loopback mode. In this mode, the recovered
clock and data output from Clock and Data Recovery on the receive path
is looped back to the jitter attenuator (if enabled) and Waveform Shaper in
transmit path.
Both Analog Loopback mode and Digital Loopback mode allow the
When the RLP bit (MAINT0, 2BH...) is set to ‘1’, the corresponding chan-
Figure-15
Slicer
Data
REMOTE LOOPBACK
Slicer
Data
Driver
Figure-16
Line
shows the process.
One of the Eight Identical Channels
One of the Eight Identical Channels
Equalizer
Adaptive
Driver
Line
shows the process.
Equalizer
Adaptive
Termination
Termination
Transmitter
Receiver
Internal
Internal
Termination
Transmitter
Termination
Internal
Receiver
Internal
Loopback
Analog
February 5, 2009
TTIPn
RTIPn
TRINGn
RRINGn
TTIPn
TRINGn
RTIPn
RRINGn

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