IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 54
IDT82P5088BBG
Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82P5088BBG.pdf
(81 pages)
Specifications of IDT82P5088BBG
Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P5088BBG
Manufacturer:
IDT
Quantity:
170
Company:
Part Number:
IDT82P5088BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT82P5088BBG
Manufacturer:
IDT
Quantity:
20 000
Table-58 INTES: Interrupt Trigger Edges Select Register
PROGRAMMING INFORMATION
IDT82P5088
NLPD_IES
PRBS_IES
NLPA_IES
TCLK_IES
LOS_IES
AIS_IES
Symbol
DF_IES
-
(R/W, Address = X35H)
Bit
4
7
6
5
3
2
1
0
Default
0
0
0
0
0
0
0
0
Reserved.
This bit determines the Inband Loopback Activate Code interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the NLPA_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the NLPA_S bit in the STAT0
status register.
This bit determines the Inband Loopback Deactivate Code interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the NLPD_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the NLPD_S bit in the STAT0
status register.
This bit determines the PRBS/QRSS synchronization status interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the PRBS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in the STAT0
status register.
This bit determines the TCLK Loss interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in the
STAT0 status register.
This bit determines the Driver Failure interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the DF_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in the STAT0
status register.
This bit determines the AIS interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the AIS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in the STAT0
status register.
This bit determines the LOS interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the LOS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in the STAT0
status register.
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
54
Description
February 5, 2009