IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 37

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

3.9
registers in the device. The interface consists of Serial Peripheral Inter-
face (SPI) and parallel microprocessor interface.
3.9.1
set in SPI mode.
with the microprocessor. A falling transition on CS pin indicates the start
of a read/write operation, and a rising transition indicates the end of the
Instruction
3.9.2
parallel mode. In this mode, the interface is compatible with the Motorola
and the Intel microprocessor, which is selected by the MPM pin. The
IDT82P5088 uses separate address bus and data bus. The mode selec-
tion and the interfaced pin are tabularized in
Instruction
FUNCTIONAL DESCRIPTION
IDT82P5088
SCLK
SCLK
SDO
SDO
SDI
SDI
CS
CS
The microprocessor interface provides access to read and write the
Pull the SPIEN pin to high, and the microprocessor interface will be
In this mode, only the CS, SCLK, SDI and SDO pins are interfaced
Pull the SPIEN pin to low, the microprocessor interface will be set in
MICROPROCESSOR INTERFACE
SPI Mode
Parallel Microprocessor Interface
0
0
X
X
1
1
X
X
2
2
X A11 A10 A9
X A11 A10
3
3
4
4
High Impedance
High Impedance
5
5
Table
A9
Figure-22 Write Operation In SPI Mode
Figure-21 Read Operation In SPI Mode
6
6
25.
A8
A8
7
7
Register Address
A7 A6 A5 A4 A3 A2 A1
A7 A6 A5 A4 A3 A2 A1
8
Register Address
8
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
9
9
10
10
11 12 13 14 15 16 17 18 19 20 21 22 23
11 12 13 14 15 16 17 18 19 20 21 22 23
37
operation. After the CS pin is set to low, two bytes include instruction
and address bytes on the SDI pin are input to the device on the rising
edge of the SCLK pin. First byte consists of one instruction bit at MSB
and three address bits at LSB, and the second byte is low 8 address
bits. If the MSB is ‘1’, it is read operation. If the MSB is ‘0’, it is write
operation. If the device is in read operation, the data read from the spec-
ified register is output on the SDO pin on the falling edge of the SCLK
(refer to
the specified register is input on the SDI pin following the address byte
(refer to
Table-25 Parallel Microprocessor Interface
Pin MPM
High
Low
Figure
Figure
Microprocessor Interface
A0
A0
22).
21). If the device is in write operation, the data written to
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2 D1
Motorola
Intel
Data Byte
Don't Care
CS, RD, WR, A[10:0], D[7:0]
CS, DS, RW, A[10:0], D[7:0]
Interfaced Pin
February 5, 2009
D0
D0