IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 39

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

3.11 GENERAL PURPOSE I/O
GPIO0. These two pins can be considered as digital Input or Output port
by the DIR1 bit (GPIO, 06H) and DIR0 bit (GPIO, 06H) respectively. If the
GPIO1 and GPIO0 are configured as Input port, the LEVEL1 bit (GPIO,
06H) and the LEVEL0 bit (GPIO, 06H) are used to reflect the level of the
GPIO1 pin and the GPIO0 pin respectively. If the GPIO1 and GPIO0 are
configured as Output port, the content in the LEVEL1 bit and LEVEL0 bit
determines the logic value of GPIO1 pin and GPIO0 pin respectively.
3.12 RESET OPERATION
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FUNCTIONAL DESCRIPTION
IDT82P5088
The IDT82P5088 provides two general purpose digital I/O pins: GPIO1,
The chip can be reset in two ways:
Software Reset: Writing to the RST register (04H) will reset the chip
in 1 us.
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
39
•
flip-flops are reset, and all the registers are initialized to default values.
When performing a software reset, the TE_MODE bit (T1E1 mode, 20H...)
will not be reset and stay with the set value.
3.13 POWER SUPPLY
After reset, all drivers output are in high impedance state, all the internal
This chip uses 3.3 V and 1.8 V power supply.
Hardware Reset: Asserting the RESET pin low for a minimum of 100
ns will reset the chip.
During Hardware Reset, the device requires an active clock on MCLK.
For T1/J1 operation, bit TE_MODE(T1E1 mode, 20H...) is set after
reset. Before accessing any other registers a delay of 50 us is required
to allow the internal clocking to be settled.
February 5, 2009