IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 17

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IDT82P5088BBG

Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82P5088BBG

Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-

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3
3.1
channel T1/J1 LIU. In E1 application, the TEMODE bit (T1E1 mode, 20H...)
should be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’.
3.2
Encoder, an Jitter Attenuator, a Waveform Shaper, a set of LBOs, a Line
Driver and a Programmable Transmit Termination.
3.2.1
pin and TDNn pin. In E1 mode, the TCLKn is a 2.048 MHz clock. In T1/J1
mode, the TCLKn is a 1.544 MHz clock. If the TCLKn is missing for more
than 70 MCLK cycles, an interrupt will be generated if it is not masked.
edge of TCLKn. The active edge of TCLKn can be selected by the
TCLK_SEL bit (TCF0, 22H...). And the active level of the data on TDn/TDPn
and TDNn can be selected by the TD_INV bit (TCF0, 22H...).
ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used
for transmitting data and the T_MD[1] bit (TCF0, 22H...) should be set to
‘0’. In Dual Rail Mode, both TDPn and TDNn pins are used for transmitting
data, the T_MD[1] bit (TCF0, 22H...) should be set to ‘1’.
3.2.2
selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 22H...).
figured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 22H...).
T_MD[1] is ‘1’), the Encoder is by-passed. In the Dual Rail mode, a logic ‘1’
on the TDPn pin and a logic ‘0’ on the TDNn pin results in a negative pulse
on the TTIPn/TRINGn; a logic ‘0’ on TDPn pin and a logic ‘1’ on TDNn pin
results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn
are logic ‘1’ or logic ‘0’, the TTIPn/TRINGn outputs a space (Refer to
TDPn/TDNn Pin
3.2.3
before sending it. The first is to use preset pulse templates for short haul
FUNCTIONAL DESCRIPTION
IDT82P5088
The IDT82P5088 can be used as an eight-channel E1 LIU or an eight-
The transmit path of each channel of the IDT82P5088 consists of an
The transmit path system interface consists of TCLKn pin, TDn/TDPn
Transmit data is sampled on the TDn/TDPn and TDNn pins by the active
The transmit data from the system side can be provided in two different
When T1/J1 mode is selected, in Single Rail mode, the Encoder can be
When E1 mode is selected, in Single Rail mode, the Encoder can be con-
In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit
The IDT82P5088 provides three ways of manipulating the pulse shape
FUNCTIONAL DESCRIPTION
T1/E1/J1 MODE SELECTION
TRANSMIT PATH
TRANSMIT PATH SYSTEM INTERFACE
ENCODER
PULSE SHAPER
Description).
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
TDn,
17
application, the second is to use LBO (Line Build Out) for long haul appli-
cation and the other way is to use user-programmable arbitrary waveform
template.
3.2.3.1 Preset Pulse Templates
the G.703 and the measuring diagram is shown in Figure-4. In internal
impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0]
bits (TCF1, 23H...) should be set to ‘0000’; if the cable impedance is 120
Ω, the PULS[3:0] bits (TCF1, 23H...) should be set to ‘0001’. In external
impedance matching mode, for both E1/75 Ω and E1/120 Ω cable imped-
ance, PULS[3:0] should be set to ‘0001’.
the T1.102 and the measuring diagram is shown in
meets the requirement of G.703, 2001. The cable length is divided into five
grades, and there are five pulse templates used for each of the cable length.
The pulse template is selected by PULS[3:0] bits (TCF1, 23H...).
Note: 1. For R
For E1 applications, the pulse shape is shown in
For T1 applications, the pulse shape is shown in
2. For R
Figure-3 E1 Waveform Template Diagram
IDT82P5088
Figure-4 E1 Pulse Template Test Circuit
1 .2 0
1 .0 0
0 .6 0
0 .4 0
-0 .2 0
0 .8 0
0 .2 0
0 .0 0
-0 .6
LOAD
LOAD
= 75 Ω (nom), V
=120 Ω (nom), V
- 0 .4
TRINGn
TTIPn
- 0 .2
out
T im e in U n it In te rv a ls
out
(Peak)=2.37V (nom)
(Peak)=3.00V (nom)
0
0 .2
R
Figure-3
Figure-5
February 5, 2009
LOAD
Figure-6.
0 .4
according to
according to
V
This also
0 .6
OUT

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