IDT77010L155PQF IDT, Integrated Device Technology Inc, IDT77010L155PQF Datasheet - Page 7

• Manufacturer Part Number: IDT77010L155PQF
• Description: TRANSLATION DEVICE DPI 80-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77010L155PQF

• Applications: Data Interface
• Interface: DPI, UTOPIA
• Voltage - Supply: 3.3V, 5V
• Package / Case: 80-MQFP, 80-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77010L155PQF

UTOPIA Receive Interface Operation
UTOPIA Receive Interface Operation
UTOPIA Receive Interface Operation
UTOPIA Receive Interface Operation
UTOPIA PHY device. The UTOPIA Receive Clock (RCLK) is a contin-
uous clock generated from the System Clock (SYSCLK) and is half the
frequency of the DPI Receive Clock (DRxCLK).
ferred over the Receive Data bus (RxDATA[7:0]), which is 8-bits wide.
Receive Parity (RxPRTY) is not supported by the 77010, nor does it
calculate the HEC in the header field.
after detecting a high Receive Cell Available (RCLAV), if it is not
executing a control cell. Refer to the UTOPIA Receive Flow Control
section for description on muxing internally generated control cells with
UTOPIA receive cells.
receive the entire cell without interruption.
UTOPIA Receive Flow Control
UTOPIA Receive Flow Control
UTOPIA Receive Flow Control
UTOPIA Receive Flow Control
media. This provides additional bandwidth for the insertion of control
cells.
and RENB are de-asserted and a cell transfer is not taking place. When
a control cell is inserted RENB is de-asserted high for 55 RCLK cycles,
which prevents the PHY from transferring a cell. During this 55 clock
period the 77010 inserts the control cell and sends it out to the DPI
receive interface.
IDT77010
UTOPIA cell level handshake is used to receive an ATM cell from a
The receive cell header, including the HEC, and payload are trans-
The 77010 will assert Receive Enable (RENB) low two clock cycles
Once Receive Start Of Cell (RSOC) is detected the 77010 will
The UTOPIA data rate is higher than the cell rate on the transport
The 77010 will only generate an internal control cell when RCLAV
PHY
PHY
TCLAV
UTOPIA
Transmit bus
UTOPIA
Receive Bus
8
8
Figure 5 UTOPIA Transmit Data Flow
Figure 4 UTOPIA Receive Data Flow
UTOPIA
Interface
UTOPIA
Interface
generated status
Internally
7 of 21
Line Card Interface
cell
Control cell
filter
No back to back
receive UTOPIA status cells and internally generated control cells do not
exceed 160 Mbps.
control to function without the loss of a cell. Figure 4 shows the receive
cell muxing with the internally generated status cells.
UTOPIA Transmit Interface
UTOPIA Transmit Interface
UTOPIA Transmit Interface
UTOPIA Transmit Interface
Operation
Operation
Operation
Operation
UTOPIA PHY device. The UTOPIA Transmit Clock (TCLK) is a contin-
uous clock generated from the System Clock (SYSCLK) and is half the
frequency of the DPI Transmit Clock (DTxCLK).
(TCLAV) the 77010 will assert TENB low. One TCLK cycle after TENB
assertion the 77010 will assert Transmit Start Of Cell (TSOC) and the
first valid byte of data. TSOC is one TCLK cycle long and coincides with
the first valid byte of data (TxDATA[7:0]). When the entire cell has been
transferred the 77010 will sample TCLAV for cell availability.
77010 will continue transferring the current cell and store up to nine
bytes of the next cell in its pipeline if TCLAV is de-asserted during a cell
transfer.
the transmit UTOPIA bus.
Rx cell detector
Internally generated control cells should be paced so that the sum of
The PHY is expected to buffer at least two receive cells for the flow
UTOPIA cell level handshake is used to transfer an ATM cell to a
Two TCLK cycles after detection of a high Transmit Cell Available
The PHY will de-assert TCLAV if it cannot accept another cell. The
Control cells from the DPI interface are filtered and not forwarded to
Figure 5 shows UTOPIA transmit data flow.
Interface
Control
TxCLK
4 to 8
DPI
Receive DPI bus
4
Transmit DPI bus
Transmit DPI clock
4308 drw 05
4
4308 drw 06
June 24, 2002