MAX11607EWC+T Maxim Integrated, MAX11607EWC+T Datasheet - Page 16

• Manufacturer Part Number: MAX11607EWC+T
• Description: Analog to Digital Converters - ADC 10-Bit 4Ch 94.4sps 3.6V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11607EWC+T

• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 94.4 Ksps
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 60 dB
• Interface Type: I2C
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: WLP-12
• Maximum Power Dissipation: 1.288 W
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.048 V

The device memory contains all of the conversion results
when the MAX11606–MAX11611 release SCL. The con-
verted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from a
multichannel scan. This does not apply to the
MAX11608/MAX11609 as each provides separate pins
for AIN7 and REF. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and point to the
Low-Power, 4-/8-/12-Channel, I
10-Bit ADCs in Ultra-Small Packages
Figure 10. Internal Clock Mode Read Cycles
Figure 11. External Clock Mode Read Cycle
16
A. SINGLE CONVERSION WITH INTERNAL CLOCK
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
S
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
S
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
S
1
S
SLAVE ADDRESS
______________________________________________________________________________________
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
SLAVE ADDRESS
SLAVE ADDRESS
7
t
MASTER TO SLAVE
SLAVE TO MASTER
ACQ
7
t
ACQ1
7
7
1 1
R
A
1 1
R
A
1 1
R
1 1
R
CLOCK STRETCH
A
A
t
CONV
t
t
t
ACQ
ACQ1
CONV1
RESULT 1 (2 MSBs)
RESULT (2 MSBs)
CLOCK STRETCH
8
8
RESULT 2 MSBs
t
ACQ2
t
CONV2
8
1
A
1
A
t
CONV
t
CONV1
RESULT 2 (8 LSBs)
A
RESULT (8 LSBs)
CLOCK STRETCH
RESULT 8 LSBs
8
8
t
t
ACQN
CONVN
8
1
A
1
A
RESULT 1 ( 2MSBs)
t
ACQ2
1
A
P OR Sr
P or Sr
1
8
1
first result. Note that only the current conversion results
are read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
1
A
t
RESULT N (2 MSBs)
NUMBER OF BITS
ACQN
NUMBER OF BITS
RESULT 1 (8 LSBs) A
8
8
2
1
C,
1
A
t
CONVN
RESULT N (8MSBs)
RESULT N (8 LSBs)
8
8
1
A
RESULT N (8LSBs)
1
A
8
P OR Sr
1
1
A
P or Sr
1
NUMBER OF BITS
NUMBER OF BITS