MAX11607EWC+T Maxim Integrated, MAX11607EWC+T Datasheet - Page 5

• Manufacturer Part Number: MAX11607EWC+T
• Description: Analog to Digital Converters - ADC 10-Bit 4Ch 94.4sps 3.6V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11607EWC+T

• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 94.4 Ksps
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 60 dB
• Interface Type: I2C
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: WLP-12
• Maximum Power Dissipation: 1.288 W
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.048 V

TIMING CHARACTERISTICS (Figure 1) (continued)
(V
(MAX11607/MAX11609/MAX11611), V
wise noted. Typical values are at T
Note 1: All WLP devices are 100% production tested at T
Note 2: For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at V
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 4: Offset nulled.
Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
Note 8: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
Note 10: Measured as follows for the MAX11607/MAX11609/MAX11611:
Note 11: A master device must provide a data hold time for SDA (referred to V
Note 14: f
Note 12: The minimum value is specified at T
Note 13: C
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal after
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
DD
= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V
design and characterization.
are tested at V
offsets have been calibrated.
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit ).
and for the MAX11606/MAX11608/MAX11610, where N is the number of bits:
falling edge (see Figure 1).
SCL
PARAMETER
⎡
⎢
⎣
⎡
⎢
⎣
B
[
[
V
V
= total capacitance of one bus line in pF.
FS
FS
must meet the minimum clock low time plus the rise/fall times.
( .
( .
3 6
5 5
V
V
_______________________________________________________________________________________
( .
( .
5 5
3 6
)
)
−
−
DD
V
V
V
V
FS
FS
= 3V. All devices are configured for unipolar, single-ended inputs.
−
−
( .
( .
2 7
4 5
2 7
4 5
.
.
10-Bit ADCs in Ultra-Small Packages
V
V
A
V
V
)
)
)
)
= +25°C. See Tables 1–5 for programming notation.) (Note 1)
]
]
×
×
REF
SYMBOL
t
2
2
SU
V
V
t
t
t
RCL1
t
t
N
N
REF
RDA
REF
RCL
FCL
FDA
C
t
= 4.096V (MAX11606/MAX11608/MAX11610), f
SP
Low-Power, 4-/8-/12-Channel, I
,
−
−
STO
B
1
1
⎤
⎥
⎦
⎤
⎥
⎦
A
= +25°C.
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
(Notes 11 and 14)
DD
A
= +25°C. Specifications over temperature limits are guaranteed by
= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V
CONDITIONS
DD
DD
DD
DD
DD
to 0.7V
to 0.7V
to 0.7V
to 0.7V
to 0.7V
IL
DD
DD
DD
DD
DD
of SCL) to bridge the undefined region of SCL’s
DD
(Note 12)
P-P
= 5V and the MAX11607/MAX11609/MAX11611
.
SCL
= 1.7MHz, T
DD
.
MIN
160
20
20
20
20
20
0
A
= T
MIN
TYP
to T
MAX
MAX
160
160
160
400
80
80
10
REF
, unless other-
= 2.048V
2
UNITS
C,
pF
ns
ns
ns
ns
ns
ns
ns
5