AS1542-BTSU ams, AS1542-BTSU Datasheet - Page 17

• Manufacturer Part Number: AS1542-BTSU
• Description: Analog to Digital Converters - ADC
• Manufacturer: ams

Specifications of AS1542-BTSU

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 1 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 71 dB
• Interface Type: QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 18.4 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

AS1542
Data Sheet - D e t a i l e d D e s c r i p t i o n
Power Mode Selection
Control register bits PM1 and PM0 are used to configure the AS1542 power mode.
Table 9. Power Mode Selection via Bits PM1 and PM0
Sequencer Operation
The setting of control register bits SEQ and SHADOW sets the sequencer operation and also selects the shadow reg-
ister for programming.
Table 10. Sequencer Configuration via Bits SEQ and SHADOW
www.austriamicrosystems.com
PM1
1
0
SEQ
0
0
1
1
PM0
X
1
Normal Operation
Auto Shutdown
Mode
SHADOW
0
1
0
1
In this mode, the AS1542 remains in full power mode regardless of the status of
any of the logic inputs. This mode allows the fastest possible throughput rate.
In this mode, the AS1542 automatically enters shutdown mode at the end of
each conversion when the control register is updated. Wake-up time from
shutdown is 1µs.
Note: Ensure that 1µs has elapsed before attempting to perform a valid conver-
sion in this mode.
These settings indicate that the sequencer is not used. The analog input
channel selected for each individual conversion is determined by the
contents of the channel address bits
prior write operation. This mode of operation reflects the normal operation
of a multi-channel ADC (without the sequencer) where each write to the
AS1542 specifies the next input channel for conversion
page
These settings select the shadow register for programming. After a write
to the control register, the following write operation will load the contents
of the shadow register. This will program the sequence of channels to be
repeatedly converted each successive valid CSN falling edge (see
Table 11 on page 18
Note: The specified input channels need not be consecutive.
With these settings, the sequencer will not be interrupted upon
completion of a write operation. This allows other bits of the control
register (PM1, PM0, WEAK/TRIN, RANGE, CODING and SE/FDN) to be
altered while in a sequence without terminating the cycle.
These settings are used in conjunction with the channel address bits
ADDR3:ADDR0 to program continuous conversions on a consecutive
sequence of channels (channel 0 ... channel n) as determined by the
address bits
30 on page
18).
Revision 1.00
20).
ADDR3:ADDR0 (page 14)
and
Figure 29 on page
Description
Description
ADDR3:ADDR0 (page 14)
of the control register
19).
(see Figure 28 on
(see Figure
in each
17 - 29