AS1542-BTSU ams, AS1542-BTSU Datasheet - Page 20

• Manufacturer Part Number: AS1542-BTSU
• Description: Analog to Digital Converters - ADC
• Manufacturer: ams

Specifications of AS1542-BTSU

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 1 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 71 dB
• Interface Type: QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 18.4 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

AS1542
Data Sheet - D e t a i l e d D e s c r i p t i o n
Channel Counter Conversion (SEQ = 1, SHADOW = 1)
Figure 30
shadow register or write to the part on each serial transfer. To exit this mode of operation and revert back to the normal
mode of operation of a multi-channel ADC (as outlined in
SHADOW = 0 on the next serial transfer.
Figure 30. Bit SEQ = 1, Bit SHADOW = 1 Flowchart
Serial Interface
Figure 31
sion clock and also controls the transfer of information to and from the AS1542 during each conversion.
Figure 31. Serial Interface Timing Diagram
www.austriamicrosystems.com
DOUT
SCLK
Exit this flow whenever WRITE = 1 and NOT (SEQ = 1, SHADOW = 0)
CSN
CSN Falling
DIN
ADDR3
Edge
t
t
CSDOV
CSDOE
Tri-State
Bit WRITE = 0
shows how a sequence of consecutive channels can be converted from without having to program the
shows the detailed timing diagram for serial interfacing to the AS1542. The serial clock provides the conver-
t
WRITE
CSS
CSN Falling
Channels from Channel 0 up to and includ-
DOUT: Conversion Result from previously
Selected ADDR3:ADDR0 in the Control
Edge
1
ADDR2
Continuously Convert Consecutive
t
DS
SEQ
selected Channel
2
ing Previously
ADDR1
Sequence of
Register
ADDR3
4 ID Bits
3
ADDR0
Bit WRITE = 0
ADDR2
Use ADDR3:ADDR0
4
DOUT: Dummy Conversion Result
for Channel Counter Conversion*
DB11
Select Coding, Range, SE/FDN,
DIN: Write to Control Register;
WEAK/TRIN and Power Mode
Bit SEQ = 1, Bit SHADOW = 1
t
DOV
ADDR1
t
CH
t
CSN Falling
DH
Bit SHADOW = 0
Bit WRITE = 1;
5
Revision 1.00
Bit WRITE = 1
Bit WRITE = 0
DB10
Power On
Bit SEQ = 1
Edge
ADDR0
(see Table 5 on page 14)
Figure
t
CONVERT
6
t
DOH
Bit WRITE = 1, Bit SEQ = 1, Bit SHADOW = 0
29), verify bit
DOUT: Conversion Result from pre-
Continuously Convert the Selected
12
Channels and Allow Changes to
without Conversion Interruption
DB3
viously selected Channel
SE/FDN
Control Register
Sequence of
13
WRITE (page 14)
DB2
DC
B
t
14
CL
will determine the last channel used for
DB1
conversion. e.g.: 0101 = 5 => channel
*The binary selected channel number
0:5 will be used for conversion.
DC
15
t
DOD
DB0
= 1 and bits SEQ and
DC
Bit SHADOW = 0
Bit WRITE = 1,
16
Bit SEQ = 1,
t
CSH
DC = Don’t Care
Tri-State
t
QUIET
20 - 29