LCMXO2280C-5FTN256C Lattice, LCMXO2280C-5FTN256C Datasheet - Page 14
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LCMXO2280C-5FTN256C
Manufacturer Part Number
LCMXO2280C-5FTN256C
Description
CPLD - Complex Programmable Logic Devices 2280 LUTS 211 I/O
Manufacturer
Lattice
Datasheet
1.LCMXO1200C-5TN100C.pdf
(96 pages)
Specifications of LCMXO2280C-5FTN256C
Rohs
yes
Memory Type
SRAM
Number Of Macrocells
1140
Delay Time
3.6 ns
Number Of Programmable I/os
211
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Package / Case
CSBGA-132
Mounting Style
SMD/SMT
Factory Pack Quantity
450
Supply Current
23 mA
Supply Voltage - Max
3.465 V
Supply Voltage - Min
1.71 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2280C-5FTN256C
Manufacturer:
Lattice
Quantity:
30
Company:
Part Number:
LCMXO2280C-5FTN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LCMXO2280C-5FTN256C-4I
Manufacturer:
TI
Quantity:
286
Lattice Semiconductor
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual, Pseudo-Dual Port and FIFO Modes
Figure 2-12 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM
modes, the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the memory array output.
Figure 2-12. sysMEM Memory Primitives
AD[12:0]
AD[12:0]
DI[35:0]
CS[2:0]
CS[2:0]
RST
RST
CLK
CLK
WE
CE
CE
Single Port RAM
ROM
EBR
EBR
DI[35:0]
CLKW
RSTA
CEW
WE
DO[35:0]
DO[35:0]
EBR
FIFO
2-11
ADW[12:0]
DOA[17:0]
ADA[12:0]
DIA[17:0]
CSA[2:0]
DI[35:0]
CS[2:0]
CLKW
CLKA
RSTA
CEW
WEA
CEA
RST
WE
Pseudo-Dual Port RAM
True Dual Port RAM
DO[35:0]
CLKR
RSTB
RE
RCE
FF
AF
EF
AE
EBR
EBR
MachXO Family Data Sheet
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADR[12:0]
DO[35:0]
CER
CLKR
Architecture