M4A5-64/32-55VNC Lattice, M4A5-64/32-55VNC Datasheet - Page 12
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
M4A5-64/32-55VNC
Manufacturer Part Number
M4A5-64/32-55VNC
Description
CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
Manufacturer
Lattice
Datasheet
1.M4A5-19296-10VNI.pdf
(62 pages)
Specifications of M4A5-64/32-55VNC
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
167 MHz
Delay Time
5 ns
Number Of Programmable I/os
256
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
800
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A5-64/32-55VNC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
M4A5-64/32-55VNC48
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Note:
1. Polarity of CLK/LE can be programmed
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the
D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided
between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used
on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be
programmed.
The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the
additional choice of either polarity of an individual product term clock in the asynchronous mode.
The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and
preset are provided, each driven by a product term common to the entire PAL block.
12
D-type Register
T-type Register
D-type Latch
Product Terms
Initialization
PAL-Block
Configuration
a. Power-up reset
Power-Up
Reset
Figure 7. Synchronous Mode Initialization Configurations
D/T/L
AP
Table 8. Register/Latch Operation
Input(s)
AR
Q
D=X
D=0
D=1
D=X
D=0
D=1
T=X
T=0
T=1
ispMACH 4A Family
17466G-012
Product Terms
Initialization
PAL-Block
0,1, ↓ (↑)
0, 1, ↓ (↑)
CLK/LE
↑ (↓)
↑ (↓)
↑ (↓)
↑ (↓)
1(0)
0(1)
0(1)
1
Power-Up
b. Power-up preset
Preset
D/L
AP
Q+
Q
Q
Q
Q
Q
0
1
0
1
17466G-013
AR
Q