M4A5-64/32-55VNC Lattice, M4A5-64/32-55VNC Datasheet - Page 38
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M4A5-64/32-55VNC
Manufacturer Part Number
M4A5-64/32-55VNC
Description
CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
Manufacturer
Lattice
Datasheet
1.M4A5-19296-10VNI.pdf
(62 pages)
Specifications of M4A5-64/32-55VNC
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
167 MHz
Delay Time
5 ns
Number Of Programmable I/os
256
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
800
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A5-64/32-55VNC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
M4A5-64/32-55VNC48
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES
38
Combinatorial Delay:
t
t
Registered Delays:
t
t
t
t
t
t
t
t
t
t
Latched Delays:
t
t
t
t
t
t
t
t
t
t
Input Register Delays:
t
t
t
Input Latch Delays:
t
t
t
t
PDi
PD
SS
SST
SA
SAT
HS
HA
COSi
COS
COAi
COA
SSL
SAL
HSL
HAL
PDLi
PDL
GOSi
GOS
GOAi
GOA
SIRS
HIRS
ICOSi
SIL
HIL
IGOSi
PDILi
Internal combinatorial propagation
delay
Combinatorial propagation delay
Synchronous clock setup time, D-type
register
Synchronous clock setup time, T-type
register
Asynchronous clock setup time, D-type
register
Asynchronous clock setup time, T-type
register
Synchronous clock hold time
Asynchronous clock hold time
Synchronous clock to internal output
Synchronous clock to output
Asynchronous clock to internal output
Asynchronous clock to output
Synchronous latch setup time
Asynchronous latch setup time
Synchronous latch hold time
Asynchronous latch hold time
Transparent latch to internal output
Propagation delay through transparent
latch to output
Synchronous gate to internal output
Synchronous gate to output
Asynchronous gate to internal output
Asynchronous gate to output
Input register setup time
Input register hold time
Input register clock to internal feedback
Input latch setup time
Input latch hold time
Input latch gate to internal feedback
Transparent input latch to internal
feedback
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
3.0
4.0
2.5
3.0
0.0
2.5
4.0
3.0
0.0
3.0
1.5
2.5
1.5
2.5
-5
3.5
5.0
2.5
4.0
5.0
6.5
5.5
7.0
3.0
4.5
6.0
7.5
3.0
3.5
1.5
3.5
4.0
2.5
3.0
0.0
2.5
4.0
3.0
0.0
3.0
1.5
2.5
1.5
2.5
ispMACH 4A Family
-55
4.0
4.0
7.0
4.5
1.5
5.5
2.5
5.0
6.5
5.5
3.0
6.0
7.5
3.0
3.5
3.5
4.0
2.5
3.0
0.0
2.5
4.0
3.5
0.0
3.5
2.0
3.0
1.5
2.5
-6
4.3
6.0
2.8
4.5
5.0
6.8
5.8
7.5
3.0
4.8
6.0
7.8
3.0
3.8
1.5
3.5
4.0
3.0
3.5
0.0
3.0
4.5
3.5
0.0
3.5
2.0
3.0
2.0
3.0
-65
4.5
6.5
3.0
5.0
5.0
7.0
6.0
8.0
3.0
5.0
6.0
8.0
3.0
4.0
1.5
5.0
6.0
3.5
4.5
0.0
3.5
6.0
4.0
0.0
4.0
2.0
3.0
2.0
3.0
-7
10.0
11.0
5.0
7.5
3.0
5.5
6.0
8.5
7.5
3.5
6.0
8.5
3.5
4.0
2.0
5.5
6.5
4.0
5.0
0.0
4.0
7.0
4.0
0.0
4.0
2.0
3.0
2.0
3.0
-10
10.0
11.0
12.0
10.0
13.0
7.0
3.0
6.0
8.0
9.0
4.5
7.5
4.5
4.0
2.0
7.0
8.0
5.0
6.0
0.0
5.0
8.0
5.0
0.0
5.0
2.0
3.0
2.0
3.0
-12
12.0
10.0
13.0
11.0
14.0
10.0
13.0
16.0
9.0
3.5
6.5
7.0
6.0
4.0
2.0
1
10.0
11.0
10.0
8.0
9.0
0.0
8.0
8.0
0.0
8.0
2.0
4.0
2.0
4.0
-14
11.0
14.0
12.0
15.0
12.0
15.0
11.0
15.0
18.0
3.5
6.5
8.0
6.0
5.0
2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns