MAX159ACUA+T Maxim Integrated, MAX159ACUA+T Datasheet - Page 4

• Manufacturer Part Number: MAX159ACUA+T
• Description: Analog to Digital Converters - ADC 10-Bit 108ksps 5.25V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX159ACUA+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 108 KSPs
• Resolution: 10 bit
• Input Type: Pseudo-Differential
• Snr: No
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX
• Maximum Power Dissipation: 727 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 5.25 V

TIMING CHARACTERISTICS (Figure 7)
(V
CH- = GND for MAX159, T
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
ELECTRICAL CHARACTERISTICS (continued)
(V
CH- = GND for MAX159, T
4
Note 1: Tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
Note 3: Offset nulled.
Note 4: The on channel is grounded; the sine wave is applied to off channel (MAX157 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to V
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as V
POWER REQUIREMENTS
POWER REQUIREMENTS
Wake-Up Time
CS/SHDN Fall to Output Enable
CS/SHDN Rise to Output
Disable
SCLK Fall to Output Data Valid
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK to CS/SHDN Setup
CS/SHDN Pulse Width
Positive Supply Voltage
Positive Supply Current
Positive Supply Current
Power-Supply Rejection
(Note 9)
DD
DD
_______________________________________________________________________________________
= +2.7V to +5.25V, V
= +2.7V to +5.25V, V
calibrated.
PARAMETER
PARAMETER
DD
= +2.7V.
FS
(2.7V) - V
A
A
= T
= T
REF
REF
MIN
MIN
= 2.5V, 0.1µF capacitor at REF, f
= 2.5V, 0.1µF capacitor at REF, f
SYMBOL
SYMBOL
FS
to T
to T
t
t
f
SCLKS
WAKE
(5.25V).
SCLK
V
PSR
t
t
I
I
t
t
t
t
DO
CH
DD
DD
DV
CL
CS
TR
MAX
MAX
DD
, unless otherwise noted. Typical values are at T
, unless otherwise noted. Typical values are at T
C
C
C
External clock
Internal clock, SCLK for data transfer only
External clock
Internal clock, SCLK for data transfer only
(Note 8)
External clock
Internal clock, SCLK for data transfer only
(Note 8)
Operating mode
Shutdown, CS/SHDN = GND
V
DD
L
L
L
= 100pF (Figure 1)
= 100pF (Figure 1)
= 100pF
= 2.7V to 5.25V, full-scale input
CONDITIONS
CONDITIONS
SCLK
SCLK
DD
(MAX159 only).
= 2.17MHz, 16 clocks/conversion cycle (108ksps),
= 2.17MHz, 16 clocks/conversion cycle (108ksps),
A
A
= +25°C.)
= +25°C.)
+2.7
MIN
MIN
215
215
2.5
0.1
20
50
50
60
60
0
±0.15
TYP
TYP
0.9
0.2
+5.25
MAX
MAX
2.17
120
120
120
2.0
5
5
UNITS
UNITS
MHz
mA
mV
µA
µs
ns
ns
ns
ns
ns
ns
ns
V