ispLSI 1016-80LT44 Lattice, ispLSI 1016-80LT44 Datasheet - Page 3

• Manufacturer Part Number: ispLSI 1016-80LT44
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 1016-80LT44

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Maximum Operating Frequency: 100 MHz
• Delay Time: 20 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 800
• Supply Current: 150 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

Figure 1. ispLSI 1016 Functional Block Diagram
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional I/O pin with
3-state control.
selectable, active high or active low. The signal levels are
TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The ispLSI
1016 device contains two of these Megablocks.
Functional Block Diagram
SDO/IN 1
SDI/IN 0
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ispEN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
Additionally, all outputs are polarity
Megablock
Logic Blocks
Generic
(GLBs)
A0
A1
A2
A3
A4
A5
A6
A7
Routing
Global
(GRP)
Pool
2
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1016 device are selected using the
Clock Distribution Network. Three dedicated clock pins
(Y0, Y1 and Y2) are brought into the distribution network,
and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0
and IOCLK 1) are provided to route clocks to the GLBs
and I/O cells. The Clock Distribution Network can also be
driven from a special clock GLB (B0 on the ispLSI 1016
device). The logic of this GLB allows the user to create an
internal clock from a combination of internal signals
within the device.
Specifications ispLSI 1016
Y1/RESET*
SCLK/Y2
Y0
Distribution
Network
B 0
B7
B6
B5
B4
B3
B2
B1
Clock
*Note: Y1 and RESET
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
are multiplexed
on the same pin
0139B(1a)-isp.eps
IN 3
MODE/IN 2
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16