S9S12G96F0VLH Freescale Semiconductor, S9S12G96F0VLH Datasheet - Page 559
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S9S12G96F0VLH
Manufacturer Part Number
S9S12G96F0VLH
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0VLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0VLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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16.3.2.6
Writes to this register will abort current conversion sequence and start a new conversion sequence. If the
external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting
of a conversion sequence which will then occur on each trigger event. Start of conversion means the
beginning of the sampling phase.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0005
Reset
SCAN
Field
SC
6
5
W
R
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD,
CC, CB and CA of ATDCTL5.
0 Special channel conversions disabled
1 Special channel conversions enabled
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once. If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect,
thus the external trigger always starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
ATD Control Register 5 (ATDCTL5)
0
0
7
= Unimplemented or Reserved
SMP2
SC
0
6
1
Figure 16-8. ATD Control Register 5 (ATDCTL5)
Table 16-14. ATDCTL5 Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
SMP1
SCAN
Table 16-13. Sample Time Select
Table 16-15
1
0
5
SMP0
lists the coding.
MULT
1
0
4
Description
ATD Clock Cycles
CD
0
3
Sample Time
in Number of
24
Analog-to-Digital Converter (ADC12B16CV2)
CC
0
2
CB
0
1
CA
0
0
561
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