S9S12G96F0VLH Freescale Semiconductor, S9S12G96F0VLH Datasheet - Page 656
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S9S12G96F0VLH
Manufacturer Part Number
S9S12G96F0VLH
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0VLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0VLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Pulse-Width Modulator (S12PWM8B8CV2)
On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high.
There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an
edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.
19.4.2.2
Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown
on the block diagram
output flip flop. When one of the bits in the PWMPOL register is set, the associated PWM channel output
is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the
polarity bit is zero, the output starts low and then goes high when the duty count is reached.
19.4.2.3
Dedicated period and duty registers exist for each channel and are double buffered so that if they change
while the channel is enabled, the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period and duty registers will go
directly to the latches as well as the buffer.
A change in duty or period can be forced into effect “immediately” by writing the new value to the duty
and/or period registers and then writing to the counter. This forces the counter to reset and the new duty
and/or period values to be latched. In addition, since the counter is readable, it is possible to know where
the count is with respect to the duty value and software can be used to make adjustments
19.4.2.4
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see
Section 19.4.1, “PWM Clock Select”
two registers, a duty register and a period register as shown in
matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change
state. A match between the PWM counter and the period register behaves differently depending on what
output mode is selected as shown in
Outputs”
658
•
•
•
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
and
PWM Polarity
PWM Period and Duty
PWM Timer Counters
Section 19.4.2.6, “Center Aligned
When forcing a new period or duty into effect immediately, an irregular
PWM cycle can occur.
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time.
Figure 19-16
MC9S12G Family Reference Manual,
as a mux select of either the Q output or the Q output of the PWM
Figure 19-16
for the available clock sources and rates). The counter compares to
Outputs”.
NOTE
and described in
Figure
Rev.1.23
Section 19.4.2.5, “Left Aligned
19-16. When the PWM counter
Freescale Semiconductor
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