S9S12G96F0VLL Freescale Semiconductor, S9S12G96F0VLL Datasheet - Page 236
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S9S12G96F0VLL
Manufacturer Part Number
S9S12G96F0VLL
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0VLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0VLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
1
Port Integration Module (S12GPIMV1)
2.4.3.48
238
Address 0x026F (G1, G2)
Address 0x026F (G3)
Read: Anytime
Write: Anytime
Read: Anytime
Write: Anytime, write 1 to clear
Field
Field
PIEJ
PIFJ
Reset
Reset
7-0
7-0
W
W
R
R
Port J interrupt enable—
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Port J interrupt flag—
This flag asserts after a valid active edge was detected on the related pin (see
Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will
occur if the associated interrupt enable bit is set.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred
0 No active edge occurred
PIFJ7
Port J Interrupt Flag Register (PIFJ)
0
0
0
7
7
PIFJ6
0
0
0
6
6
Figure 2-48. Port J Interrupt Flag Register (PIFJ)
Table 2-73. PIEJ Register Field Descriptions
Table 2-74. PIFJ Register Field Descriptions
MC9S12G Family Reference Manual,
PIFJ5
0
0
0
5
5
PIFJ4
0
0
0
4
4
Description
Description
PIFJ3
PIFJ3
3
0
3
0
Rev.1.23
PIFJ2
PIFJ2
0
0
2
2
Section 2.5.4.2, “Pin Interrupts and
Freescale Semiconductor
Access: User read/write
Access: User read/write
PIFJ1
PIFJ1
0
0
1
1
PIFJ0
PIFJ0
0
0
0
0
1
1
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