S9S12G96F0VLL Freescale Semiconductor, S9S12G96F0VLL Datasheet - Page 737
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S9S12G96F0VLL
Manufacturer Part Number
S9S12G96F0VLL
Description
16-bit Microcontrollers - MCU 16BIT 96K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G96F0VLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
96 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G96F0VLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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22.3.2.5
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0007
TSFRZ
TFFCA
TSWAI
Reset
PRNT
Field
TEN
7
6
5
4
3
W
R
RESERVED RESERVED
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is
generated by the timer prescaler.
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU
TSWAI also affects pulse accumulator.
Timer Stops While in Freeze Mode
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
TSFRZ does not stop the pulse accumulator.
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)
Precision Timer
0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
This bit is writable only once out of reset.
Timer Toggle On Overflow Register 1 (TTOV)
0
7
out of wait.
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF flag. This has the advantage of eliminating software overhead in a
separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses.
selection.
all bits.
Figure 22-9. Timer Toggle On Overflow Register 1 (TTOV)
0
6
MC9S12G Family Reference Manual, Rev.1.23
Table 22-4. TSCR1 Field Descriptions
TOV5
0
5
TOV4
0
4
Description
TOV3
0
3
TOV2
0
2
Timer Module (TIM16B6CV3)
TOV1
0
1
TOV0
0
0
739
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