MAX1296AEEG-T Maxim Integrated, MAX1296AEEG-T Datasheet - Page 7

• Manufacturer Part Number: MAX1296AEEG-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1296AEEG-T

• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 420 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

MAX1294
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
with +2.5V Reference and Parallel Interface
PIN
MAX1296
10
11
12
13
14
15
16
17
18
19
20
—
—
—
—
1
2
3
4
5
6
7
8
9
_______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
REFADJ
NAME
COM
GND
CLK
CH5
CH4
CH3
CH2
CH1
CH0
INT
WR
RD
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CS
Three-State Digital Output (D9)
Three-State Digital Output (D8)
Three-State Digital I/O Line (D7)
Three-State Digital I/O Line (D6)
Three-State Digital I/O Line (D5)
Three-State Digital I/O Line (D4)
Three-State Digital I/O Line (D3)
Three-State Digital I/O Line (D2)
Three-State Digital I/O Line (D1)
Three-State Digital I/O Line (D0)
INT goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read
operation on the data bus.
Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conver-
sion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
In internal clock mode, connect this pin to either V
Active-Low Chip Select. When CS is high, digital outputs (INT, D11–D0) are high
impedance.
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5 LSB during conversion.
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01µF capacitor. When using an external reference, connect REFADJ to V
disable the internal bandgap reference.
FUNCTION
DD
or GND.
Pin Description
DD
to
7