MAXQ8913X-0000+ Maxim Integrated, MAXQ8913X-0000+ Datasheet - Page 15

• Manufacturer Part Number: MAXQ8913X-0000+
• Description: 16-bit Microcontrollers - MCU 16-Bit Mxd Sgnl MCU w/Op Amp ADC & DAC
• Manufacturer: Maxim Integrated

Specifications of MAXQ8913X-0000+

• Rohs: yes
• Core: RISC
• Processor Series: MAXQ8913
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: WLP-58
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 7
• Interface Type: I2C, SPI, USART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Program Memory Type: Flash
• Part # Aliases: 90-08913+D02

16-Bit, Mixed-Signal Microcontroller with Op Amps,
PIN
M1
M9
M7
C8
D7
D9
H9
H7
N6
K7
N8
E6
J2
F9
L8
J6
ADC, and DACs for All-in-One Servo Loop Control
P.0.0/INT0/
P0.1/INT1/
P0.2/INT2/
P0.3/INT3/
P0.4/INT4/
P0.5/INT5/
HFXOUT
SYNCIN
NAME
HFXIN
DAC1
DAC2
SCLK
RIN+
SSEL
LIN+
RIN-
TCK
TMS
TDO
LIN-
RST
TDI
______________________________________________________________________________________
DAC1 Output. Negative DAC output voltage to drive the right Class D amplifier.
DAC1 Buffer Output. Positive terminal of the differential DAC1’s output buffered signal.
DAC2 Buffer Output. Positive terminal of the differential DAC2’s output buffered signal.
DAC2 Output. Positive DAC output voltage to drive the left Class D amplifier.
DAC2 Output. Negative DAC output voltage to drive the left Class D amplifier.
DAC1 Output. Positive DAC output voltage to drive the right Class D amplifier.
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins
executing from the reset vector when released. The pin includes a pullup current source and should
be driven by an open-drain external source capable of sinking in excess of 4mA. This pin is driven
low as an output when an internal reset condition occurs.
High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT
as the high-frequency system clock. Alternatively, HFXIN is the input for an external high-frequency
CMOS clock source when HFXOUT is floating.
High-Frequency Crystal Output. Connect an external crystal or resonator between HFXIN and HFXOUT
as the high-frequency system clock. Alternatively, float HFXOUT when an external high-frequency
CMOS clock source is connected to the HFXIN pin.
SYNCIN Clock. This pin acts as the input clock to the Class D amplifier’s sawtooth generator.
SYNCIN is a divided system clock with the divide ratio set by programmable bits.
P0.0 I/O with Interrupt or JTAG Test Clock. This pin defaults as an input with weak pullup after a reset
and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special function
disables the general-purpose I/O on the pin and makes the pin function as the test clock input. Note
that the JTAG function can be disabled using the TAP bit in the SC register.
P0.1 I/O with Interrupt or JTAG Test Data In. This pin defaults as an input with a weak pullup after a
reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special
function disables the general-purpose I/O on the pin and makes the pin function as the test data
input. Note that the JTAG function can be disabled using the TAP bit in the SC register.
P0.2 I/O with Interrupt or JTAG Test Mode Select. This pin defaults as an input with a weak pullup
after a reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s
special function disables the general-purpose I/O on the pin and makes the pin function as the test
mode select. Note that the JTAG function can be disabled using the TAP bit in the SC register. The
TMS should be gated high when JTAG is disabled.
P0.3 I/O with Interrupt or JTAG Test Data Out. This pin defaults as an input with a weak pullup after a
reset and functions as a general-purpose I/O with interrupt capability. The output function of the test
data is only enabled during the TAP’s Shift_IR or Shift_DR states. Enabling the pin's special function
disables the general-purpose I/O on the pin and makes the pin function as the test data output. Note
that the JTAG function can be disabled using the TAP bit in the SC register.
P0.4 I/O with Interrupt or SPI Chip Select. This port pin functions as a bidirectional I/O pin with interrupt
capability or as the SPI chip select. This port pin defaults to an input with a weak pullup after a reset
and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit.
P0.5 I/O with Interrupt or SPI Clock. This port pin functions as a bidirectional I/O pin with interrupt
capability or as the SPI clock. This port pin defaults to an input with a weak pullup after a reset and
functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit.
GENERAL-PURPOSE I/O, SPECIAL FUNCTION PINS
CLOCK PINS
RESET PIN
FUNCTION
Pin Description (continued)
15