MAX1075ETC-T Maxim Integrated, MAX1075ETC-T Datasheet - Page 8

• Manufacturer Part Number: MAX1075ETC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1075ETC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.8 MSPs
• Resolution: 10 bit
• Input Type: Differential
• Snr: No
• Interface Type: 3-Wire, Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: External

The MAX1072/MAX1075 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 10-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1072/MAX1075.
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1072/MAX1075, which is composed of
a T/H, a comparator, and a switched-capacitor digital-to-
analog converter (DAC). The T/H enters its tracking mode
on the 14th SCLK rising edge of the previous conversion.
Upon power-up, the T/H enters its tracking mode immedi-
ately. The positive input capacitor is connected to AIN+.
The negative input capacitor is connected to AIN-. The
T/H enters its hold mode on the falling edge of CNVST
and the difference between the sampled positive and
negative input voltages is converted. The time required
for the T/H to acquire an input signal is determined by
how quickly its input capacitance is charged. If the input
signal’s source impedance is high, the acquisition time
lengthens. The acquisition time, t
1.8Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
8
_______________________________________________________________________________________
5, 11
PIN
10
12
—
1
2
3
4
6
7
8
9
True-Differential Analog Input T/H
CNVST
NAME
RGND
DOUT
SCLK
AIN+
GND
AIN-
N.C.
V
REF
EP
V
DD
L
Detailed Description
Negative Analog Input
External Reference Voltage Input. V
capacitor and a 4.7µF capacitor to RGND.
Reference Ground. Connect RGND to GND.
Positive Analog Supply Voltage (+4.75V to +5.25V). Bypass V
capacitor to GND.
No Connection
Ground. GND is internally connected to EP.
Positive Logic Supply Voltage (1.8V to V
to GND.
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
ACQ
, is the minimum
REF
time needed for the signal to be acquired. It is calculated
by the following equation:
where R
the input signal.
Note: t
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
The ADC’s input-tracking circuitry has a 20MHz small-
signal bandwidth, making it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Internal protection diodes that clamp the analog input
to V
from GND - 0.3V to V
inputs must not exceed V
accurate conversions.
sets the analog input range. Bypass REF with a 0.01µF
DD
). Bypass V
DD
FUNCTION
ACQ
and GND allow the analog input pins to swing
IN
= 200Ω, and RS is the source impedance of
is never less than 104ns and any source
t
L
ACQ
with a 0.01µF capacitor and a 10µF capacitor
≥ 8 × (RS + R
DD
DD
with a 0.01µF capacitor and a 10µF
Analog Input Protection
+ 0.3V without damage. Both
DD
or be lower than GND for
Pin Description
IN
) × 16pF
Input Bandwidth