S9S12GN16F0CFT Freescale Semiconductor, S9S12GN16F0CFT Datasheet - Page 707
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S9S12GN16F0CFT
Manufacturer Part Number
S9S12GN16F0CFT
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12GN16F0CFT.pdf
(1292 pages)
Specifications of S9S12GN16F0CFT
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
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21.3.2
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
21.3.2.1
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base +0x0000
Reserved
Reserved
Register
Reset
SPIDRL
SPTIE
0x0005
0x0006
0x0007
Field
SPIE
Name
SPE
7
6
5
W
R
Register Descriptions
SPIE
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
0 SPI interrupts disabled.
1 SPI interrupts enabled.
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
SPI Control Register 1 (SPICR1)
0
7
W
W
W
R
R
R
Bit 7
R7
T7
SPE
0
6
= Unimplemented or Reserved
Figure 21-3. SPI Control Register 1 (SPICR1)
R6
T6
MC9S12G Family Reference Manual, Rev.1.23
6
Table 21-1. SPICR1 Field Descriptions
Figure 21-2. SPI Register Summary
SPTIE
0
5
R5
T5
5
MSTR
0
4
Description
R4
T4
4
CPOL
0
3
R3
T3
3
CPHA
1
2
Serial Peripheral Interface (S12SPIV5)
R2
T2
2
SSOE
0
1
R1
T1
1
LSBFE
Bit 0
R0
T0
0
0
709
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