MAX1134BEAP-T Maxim Integrated, MAX1134BEAP-T Datasheet - Page 10

• Manufacturer Part Number: MAX1134BEAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1134BEAP-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 150 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 83 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 3.135 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.2 V

The user-programmable outputs are set to zero during
power-on reset or when RST goes low. During hardware
or software shutdown, P0, P1, and P2 are unchanged
and remain low impedance.
Start a conversion by clocking a control byte into the
device’s internal shift register. With CS low, each rising
edge on SCLK clocks a bit from DIN into the
MAX1134/MAX1135s’ internal shift register. After CS
goes low or after a conversion or calibration completes,
the first arriving logic 1 is defined as the start bit of the
control byte. Until this first start bit arrives, any number of
logic 0 bits can be clocked into DIN with no effect. If at
any time during acquisition or conversion CS is brought
high and then low again, the part is placed into a state
where it can recognize a new start bit. If a new start bit
occurs before the current conversion is complete, the
conversion is aborted and a new acquisition is initiated.
Figure 4. External Clock Mode SSTRB Detailed Timing
16-Bit ADCs, 150ksps, 3.3V Single Supply
Figure 3. Long Acquisition Mode (32 Clock Cycles) External Clock
10
SSTRB
______________________________________________________________________________________
DOUT
SCLK
DIN
STATE
CS
A/D
SSTRB
SCLK
START
IDLE
CS
1
UNI/
BIP
INT/
EXT
t
ACQ
M1
Starting a Conversion
4
M0
t
SDV
ACQUISITION
P2
P1
P0
8
P1 CLOCKED IN
14
15
The MAX1134/MAX1135 use either the external serial
clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the
MAX1134/MAX1135. Bit 5 (INT/EXT) of the control byte
programs the clock mode.
In external clock mode, the external clock not only
shifts data in and out, but also drives the ADC conver-
sion steps.
In short acquisition mode, SSTRB pulses high for one
clock period after the seventh falling edge of SCLK fol-
lowing the start bit. The MSB of the conversion is avail-
able at DOUT on the eighth falling edge of SCLK
(Figure 2).
MSB
B15
t
SSTRB
B14
B13
Internal and External Clock Modes
CONVERSION
B4
t
SSTRB
B3
29
B2
B1
LSB
B0
32
t
FILLED WITH
STR
ZEROS
External Clock
IDLE