MAX1134BEAP-T Maxim Integrated, MAX1134BEAP-T Datasheet - Page 11

• Manufacturer Part Number: MAX1134BEAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1134BEAP-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 150 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 83 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 3.135 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.2 V

Figure 5. Internal Clock Mode Timing, Short Acquisition
Figure 6. Internal Clock Mode SSTRB Detailed Timing
In long acquisition mode, when using external clock,
SSTRB pulses high for one clock period after the 15th
falling edge of SCLK following the start bit. The MSB of
the conversion is available at DOUT on the 16th falling
edge of SCLK (Figure 3).
In external clock mode, SSTRB is high impedance when
CS is high (Figure 4). CS is normally held low during the
entire conversion. If CS goes high during the conver-
sion, SCLK is ignored until CS goes low. This allows
external clock mode to be used with 8-bit bytes.
In internal clock mode, the MAX1134/MAX1135 gener-
ate their own conversion clock. This frees the micro-
processor from the burden of running the SAR
conversion clock, and allows the conversion results to
be read back at the processor’s convenience, at any
clock rate up to 4MHz.
SSTRB
DOUT
SCLK
DIN
CS
SSTRB
SCLK
START
CS
16-Bit ADCs, 150ksps, 3.3V Single Supply
1
UNI/
______________________________________________________________________________________
BIP
INT/
EXT
t
ACQ
P0 CLOCKED IN
M1
4
M0
t
CSH
P2
P1
Internal Clock
P0
t
SSTRB
8
t
CONV
NOTE
t
CONV
:
FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB is low for
a maximum of 7µs, during which time SCLK should
remain low for best noise performance. An internal reg-
ister stores data when the conversion is in progress.
SCLK clocks the data out of the internal storage regis-
ter at any time after the conversion is complete.
The MSB of the conversion is available at DOUT when
SSTRB goes high. The subsequent 15 falling edges on
SCLK shift the remaining bits out of the internal storage
register (Figure 5). CS does not need to be held low
once a conversion is started.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Figure 6 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted into
the MAX1134/MAX1135 at clock rates up to 4MHz, pro-
MSB
B15
9
B14
10
B13
t
SCK
B4
B3
21
B2
t
CSS
B1
LSB
B0
24
FILLED WITH
ZEROS
11