MAX1245BCAP Maxim Integrated, MAX1245BCAP Datasheet - Page 12

• Manufacturer Part Number: MAX1245BCAP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX1245BCAP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.375 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Factory Pack Quantity: 66
• Voltage Reference: 2.048 V

In internal clock mode, the MAX1245 generates its own
conversion clock internally. This frees the µP from the
burden of running the SAR conversion clock and allows
the conversion results to be read back at the proces-
sor’s convenience, at any clock rate from zero to
1.5MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB will be low for a maximum of 7.5µs (SHDN =
open), during which time SCLK should remain low for
best noise performance.
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
Figure 7. Detailed Serial-Interface Timing
Figure 8. External-Clock-Mode SSTRB Detailed Timing
12
______________________________________________________________________________________
SSTRB
DOUT
SCLK
SCLK
DIN
CS
CS
t
CSH
t
DV
t
CSS
t
DS
t
t
DH
SDV
•
• • •
• • •
• • •
Internal Clock
t
CL
PD0 CLOCKED IN
t
CH
• • •
• • •
• • •
• • •
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1245 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
t
SSTRB
t
DO
• • •
t
SSTRB
• • • •
• • •
t
CSH
t
TR
t
STR