MAX1245BCAP Maxim Integrated, MAX1245BCAP Datasheet - Page 7

• Manufacturer Part Number: MAX1245BCAP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX1245BCAP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.375 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Factory Pack Quantity: 66
• Voltage Reference: 2.048 V

Figure 1. Load Circuits for Enable Time
______________________________________________________________Pin Description
12, 20
DOUT
PIN
1–8
10
11
13
14
15
16
17
18
19
9
a) High-Z to V
6k
CH0–CH7
OH
SSTRB
NAME
AGND
DGND
SHDN
DOUT
SCLK
VREF
COM
V
DIN
and V
CS
DGND
DD
_______________________________________________________________________________________
OL
to V
OH
C
Sampling Analog Inputs
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1245 down to 10µA (max) supply current; oth-
erwise, the MAX1245 is fully operational. Letting SHDN be open sets the internal clock frequency to 1.5MHz.
Pulling SHDN high sets the internal clock frequency to 225kHz. See Hardware Power-Down section.
External Reference Voltage Input for analog-to-digital conversion
Positive Supply Voltage
Analog Ground
Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1245 begins the A/D con-
version and goes high when the conversion is done. In external clock mode, SSTRB pulses high for
one clock period before the MSB decision. High impedance when CS is high (external clock mode).
Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
50pF
LOAD
b) High-Z to V
DOUT
+2.375V, Low-Power, 8-Channel,
V
DD
OL
and V
6k
C
DGND
50pF
LOAD
OH
to V
OL
Figure 2. Load Circuits for Disable Time
FUNCTION
DOUT
6k
Serial 12-Bit ADC
a) V
OH
DGND
to High-Z
C
50pF
LOAD
DOUT
b) V
OL
V
to High-Z
DD
6k
C
50pF
DGND
LOAD
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