S9S12G128F0VLLR Freescale Semiconductor, S9S12G128F0VLLR Datasheet - Page 604
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S9S12G128F0VLLR
Manufacturer Part Number
S9S12G128F0VLLR
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G128F0VLLR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8192 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale’s Scalable Controller Area Network (S12MSCANV3)
18.3.2.16 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
1
18.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
606
Module Base + 0x000F
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
Write: Unimplemented
Reset:
W
R
TXERR7
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
0
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Filter”).
Figure 18-19. MSCAN Transmit Error Counter (CANTXERR)
TXERR6
= Unimplemented
6
0
MC9S12G Family Reference Manual,
TXERR5
0
5
TXERR4
NOTE
NOTE
4
0
TXERR3
0
3
Rev.1.23
TXERR2
2
0
TXERR1
Access: User read/write
Freescale Semiconductor
Section 18.3.3.1,
0
Section 18.4.3,
1
TXERR0
0
0
1
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