S9S12G64F1MLC Freescale Semiconductor, S9S12G64F1MLC Datasheet - Page 273

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S9S12G64F1MLC

Manufacturer Part Number
S9S12G64F1MLC
Description
16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G64F1MLC

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-32
Mounting Style
SMD/SMT

Available stocks

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Manufacturer
Quantity
Price
Part Number:
S9S12G64F1MLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
S12G Memory Map Controller (S12GMMCV1)
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions.
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64KB local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper 16KB
block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset and
interrupt vectors point to locations in this area or to the other unmapped pages sections of the local CPU
memory map.
Expansion of the BDM Local Address Map
PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global
address. These registers can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
The four BDMPPR Program Page index bits allow access to the full 256KB address map that can be
accessed with 18 address bits.
The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and,
in the case the CPU is executing a firmware command which uses CPU instructions, or by a BDM
hardware commands. See the BDM Block Guide for further details. (see
Figure
5-10).
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
275

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