S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 678
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S9S12G48F0MLH
Manufacturer Part Number
S9S12G48F0MLH
Description
16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G48F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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S9S12G48F0MLH
Manufacturer:
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Quantity:
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Serial Communication Interface (S12SCIV5)
20.3.2.9
Read: Anytime; reading accesses SCI receive data register
Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect
680
Module Base + 0x0006
Module Base + 0x0007
RXPOL
BRK13
TXDIR
Reset
Reset
Field
RAF
3
2
1
0
W
W
R
R
Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a
mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA
format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal
polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for
inverted polarity.
0 Normal polarity
1 Inverted polarity
Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit
respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.
0 Break character is 10 or 11 bit long
1 Break character is 13 or 14 bit long
Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to
be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire
mode of operation.
0 TXD pin to be used as an input in single-wire mode
1 TXD pin to be used as an output in single-wire mode
Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start
bit search. RAF is cleared when the receiver detects an idle character.
0 No reception in progress
1 Reception in progress
R8
R7
T7
SCI Data Registers (SCIDRH, SCIDRL)
0
0
7
7
R6
T8
T6
= Unimplemented or Reserved
0
0
6
6
Table 20-12. SCISR2 Field Descriptions (continued)
Figure 20-12. SCI Data Registers (SCIDRH)
Figure 20-13. SCI Data Registers (SCIDRL)
MC9S12G Family Reference Manual,
R5
T5
0
0
0
5
5
R4
T4
0
0
0
4
4
Description
R3
T3
0
0
0
3
3
Rev.1.23
R2
T2
0
0
0
2
2
Freescale Semiconductor
R1
T1
0
0
0
1
1
R0
T0
0
0
0
0
0
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