S9S12G48F0MLH Freescale Semiconductor, S9S12G48F0MLH Datasheet - Page 795
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S9S12G48F0MLH
Manufacturer Part Number
S9S12G48F0MLH
Description
16-bit Microcontrollers - MCU 16Bit 48KFlash 4096RAM MSCAN
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G48F0MLH
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
48 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
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24.3.2.10 EEPROM Protection Register (EEPROT)
The EEPROT register defines which EEPROM sectors are protected against program and erase operations.
1
The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents
of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in
P-Flash memory (see
EEPROM protection that will be loaded during the reset sequence, the P-Flash sector containing the
EEPROM protection byte must be unprotected, then the EEPROM protection byte must be programmed.
If a double bit fault is detected while reading the P-Flash phrase containing the EEPROM protection byte
during the reset sequence, the DPOPEN bit will be cleared and DPS bits will be set to leave the EEPROM
memory fully protected.
Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible
if any of the EEPROM sectors are protected.
Freescale Semiconductor
DPOPEN
Loaded from IFR Flash configuration field, during reset sequence.
DPS[4:0]
Offset Module Base + 0x0009
Reset
Field
4–0
7
W
R
DPOPEN
EEPROM Protection Control
0 Enables EEPROM memory protection from program and erase with protected address range defined by DPS
1 Disables EEPROM memory protection from program and erase
EEPROM Protection Size — The DPS[4:0] bits determine the size of the protected area in the EEPROM
memory as shown
F
7
1
bits
Table
= Unimplemented or Reserved
0
0
6
Figure 24-14. EEPROM Protection Register (EEPROT)
24-4) as indicated by reset condition F in
inTable 24-21
MC9S12G Family Reference Manual, Rev.1.23
Table 24-20. EEPROT Field Descriptions
0
0
5
.
F
4
1
Description
F
3
1
Table
16 KByte Flash Module (S12FTMRG16K1V1)
DPS[4:0]
F
2
1
24-21. To change the
F
1
1
F
0
1
797
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