MAX1069BEUD Maxim Integrated, MAX1069BEUD Datasheet - Page 12

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MAX1069BEUD

Manufacturer Part Number
MAX1069BEUD
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1069BEUD

Number Of Channels
1
Architecture
SAR
Conversion Rate
58 KSPs
Resolution
14 bit
Input Type
Single-Ended
Snr
84 dB
Interface Type
I2C, Serial
Operating Supply Voltage
2.7 V to 5.25 V, 4.75 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Package / Case
TSSOP-14
Maximum Power Dissipation
864 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
4.096 V
forming a digital representation of the analog input sig-
nal. During the conversion period, the MAX1069 holds
SCL low (clock stretching).
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, lengthen the
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
Figure 3. MAX1069 Simplified Functional Diagram
Figure 4. Typical Application Circuit
12
______________________________________________________________________________________
REFADJ
AGNDS
AVDD
AGND
REF
AIN
10µF
ANALOG
SOURCE
10
11
12
13
8
9
0.1µF
0.1µF
5.0V
REFERENCE
+4.096V
13
12
10
11
8
CONTROL
AVDD
REF
REFADJ
AIN
AGNDS
LOGIC
T/H
AGND
9
MAX1069
5kΩ
DGND
1
DVDD
ADD0
ADD1
ADD2
ADD3
SDA
SCL
IN
7
6
5
4
3
2
14
A
V
= 1.0
OSCILLATOR
I
INTERNAL
2
C ADDRESS IS 0110111
CLOCK
SAR
ADC
acquisition time by reducing f
vides two SCL cycles (t
hold capacitance must acquire a charge representing
the input signal. Minimize the input source impedance
(R
charge within the allotted time. R
less than 12.9kΩ for f
4MHz
REF
SOURCE
OUT
0.1µF
3.0V
R
P
MAX1069
) to allow the track-and-hold capacitance to
OUTPUT SHIFT
REGISTER
R
P
V
SDA
SCL
V
DD
SS
µC
SCL
14
6
5
4
3
2
7
1
ADD0
ADD1
ADD2
ADD3
SDA
SCL
DVDD
DGND
ACQ
= 400kHz and less than 2.4kΩ
), in which the track-and-
SCL
. The MAX1069 pro-
SOURCE
should be

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