MAX1069BEUD Maxim Integrated, MAX1069BEUD Datasheet - Page 5

• Manufacturer Part Number: MAX1069BEUD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1069BEUD

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 58 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: I2C, Serial
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 864 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

ELECTRICAL CHARACTERISTICS (continued)
(V
reference applied to REF, REFADJ = AVDD, C
Note 1: DC accuracy is tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 3: Offset nullified.
Note 4: One sample is achieved every 18 clocks in continuous conversion mode.
Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11.
Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
Note 7: ADC performance is limited by the converter’s noise floor, typically 480µV
Note 8:
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)
Serial Clock Frequency
Hold Time, (Repeated) Start
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus
Pulse Width of Spike Suppressed
AVDD
= +4.75V to +5.25V, V
f
PSRR
by power-supply rejection test.
offset have been calibrated.
t
50ns in fast mode.
SAMPLE
ACQ
PARAMETER
=
=
2
=
[
×
V (5.25V)- V (4.75V)
_______________________________________________________________________________________
⎛
⎜
⎝
FS
⎛
⎜
⎝
f
1 clocks
SCL
8
1
f
SCL
⎞
⎟
⎠
5.25V - 4.75V
DVDD
+
FS
58.6ksps, 14-Bit, 2-Wire Serial ADC
= +2.7V to +5.5V, f
AVDD
t
C
SYMBOL
t
t
t
t
t
ONV
HD,STA
SU,STA
HD,DAT
SU,DAT
SU,STO
f
t
t
t
t
SCLH
HIGH
t
RCL1
t
t
LOW
RDA
t
RCL
FDA
C
FCL
SP
= +5.0V and V
B
⎞
⎟
⎠
]
REF
-1
×
V
= 10µF, T
2
REF
(Note 11)
(Note 9)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
N
SCL
where N is the number of bits ( ).
DVDD
A
= 1.7MHz (33% duty cycle), f
= T
= +3.0V. Performance at power-supply tolerance limits is guaranteed
MIN
CONDITIONS
to T
MAX
, unless otherwise noted. Typical values are at T
P-P
in a 14-Pin TSSOP
.
14
SAMPLE
= 58.6ksps, V
MIN
160
320
120
160
160
10
10
20
20
20
20
0
TYP
REF
= +4.096V, external
MAX
150
160
160
160
400
1.7
80
80
10
A
= +25°C.)
UNITS
MHz
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5