M4-96/96-20YI Lattice, M4-96/96-20YI Datasheet - Page 11

• Manufacturer Part Number: M4-96/96-20YI
• Description: CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of M4-96/96-20YI

• Product Category: CPLD - Complex Programmable Logic Devices
• Number Of Macrocells: 96
• Delay Time: 20 nS
• Number Of Programmable I/os: 400
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: PQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 24

The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The
primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality
is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs
are HIGH.
e. T-type with programmable T polarity
c. Latch with XOR
a. D-type with XOR
L
T
G
D
AP AR
AP AR
AP AR
Figure 6. Primary Macrocell Configurations
g. Combinatorial with programmable polarity
Q
Q
Q
ispMACH 4A Family
b. D-type with programmable D polarity
d. Latch with programmable D polarity
f. Combinatorial with XOR
D
L
G
AP AR
AP AR
Q
Q
17466G-011
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