S9S12G64F0MLF Freescale Semiconductor, S9S12G64F0MLF Datasheet - Page 514
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S9S12G64F0MLF
Manufacturer Part Number
S9S12G64F0MLF
Description
16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G64F0MLF
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
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Analog-to-Digital Converter (ADC12B12CV2)
14.3.2.12 ATD Conversion Result Registers (ATDDRn)
The A/D conversion results are stored in 12 result registers. Results are always in unsigned data
representation. Left and right justification is selected using the DJM control bit in ATDCTL3.
If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must
be written with the compare values in left or right justified format depending on the actual value of the
DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be
stored there at the end of the conversion but is lost.
Attention, n is the conversion number, NOT the channel number!
Read: Anytime
Write: Anytime
14.3.2.12.1 Left Justified Result Data (DJM=0)
Table 14-21
result registers for left justified data. Compare is always done using all 12 bits of both the conversion result
and the compare value in ATDDRn.
516
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11
Reset
W
R
15
0
shows how depending on the A/D resolution the conversion result is transferred to the ATD
= Unimplemented or Reserved
For conversions not using automatic compare, results are stored in the result
registers after each conversion. In this case avoid writing to ATDDRn except
for initial values, because an A/D result might be overwritten.
14
0
Figure 14-14. Left justified ATD conversion result register (ATDDRn)
13
0
resolution
10-bit data
12-bit data
8-bit data
Table 14-21. Conversion result mapping to ATDDRn
A/D
12
0
MC9S12G Family Reference Manual,
11
0
0
0
0
DJM
Result-Bit[11:0]
10
0
Result-Bit[11:4] = conversion result,
Result-Bit[3:0]=0000
Result-Bit[11:2] = conversion result,
Result-Bit[1:0]=00
Result-Bit[11:0] = result
conversion result mapping to
0
9
NOTE
0
8
0
7
0
6
Rev.1.23
ATDDRn
0
5
4
0
0
0
3
Freescale Semiconductor
0
0
2
0
0
1
0
0
0
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