S9S12G64F0MLF Freescale Semiconductor, S9S12G64F0MLF Datasheet - Page 586

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S9S12G64F0MLF

Manufacturer Part Number
S9S12G64F0MLF
Description
16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G64F0MLF

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
64 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT

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Freescale’s Scalable Controller Area Network (S12MSCANV3)
18.2.2
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the
CAN bus:
18.2.3
A typical CAN system with MSCAN is shown in
to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defective CAN or defective stations.
18.3
This section provides a detailed description of all registers accessible in the MSCAN.
18.3.1
Figure 18-3
register address results from the addition of base address and address offset. The base address is
determined at the MCU level and can be found in the MCU memory map description. The address offset
is defined at the module level.
The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is
determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the
first address of the module address offset.
588
Memory Map and Register Definition
0 = Dominant state
1 = Recessive state
TXCAN — CAN Transmitter Output Pin
CAN System
Module Memory Map
gives an overview on all registers and their individual bits in the MSCAN memory map. The
TXCAN
CANH
CAN Controller
Transceiver
CAN node 1
(MSCAN)
MCU
MC9S12G Family Reference Manual,
CANL
RXCAN
Figure 18-2. CAN System
CAN Bus
Figure
CAN node 2
18-2. Each CAN station is connected physically
Rev.1.23
CAN node n
Freescale Semiconductor

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