MM912F634DV1AE Freescale Semiconductor, MM912F634DV1AE Datasheet - Page 145
MM912F634DV1AE
Manufacturer Part Number
MM912F634DV1AE
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AE
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MM912F634DV1AE
Manufacturer:
FREESCALE
Quantity:
20 000
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Table 189. ADC Config Register (ACR)
Table 188. Analog Digital Converter Module - Memory Map (continued)
Note:
Functional Description and Application Information
4.19.4.2
4.19.4.2.1
Offset
133.
Freescale Semiconductor
Note:
132.
ADR14 (hi)
ADR14 (lo)
ADR15 (hi)
ADR15 (lo)
Offset
Table 190. ACR - Register Field Descriptions
Register /
Reset
0xA2
0xA3
0xA4
0xA5
W
R
7 - SCIE
5 - OCE
(133)
6 - CCE
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
(132)
0x80
W
W
W
W
R
R
R
R
SCIE
Register Definition
7
0
Sequence Complete Interrupt Enable
0 - Sequence Complete Interrupt Disabled
1 - Sequence Complete Interrupt Enabled
Continuous Conversion Enable
0 - Continuous Conversion Disabled
1 - Continuous Conversion Enabled
Offset Compensation Enable
0 - Offset Compensation Disabled
1 - Offset Compensation Enabled, This feature requires the CH15 bit in the ADC Conversion Control Register (ACCR) to
be set for all conversions.
ADC Config Register (ACR)
ADCRST is strongly recommended to be set during D2D clock frequency changes.
Bit 7
ADR14[1:0]
ADR15[1:0]
CCE
6
0
6
OCE
0
5
5
ADCRST
NOTE
0
4
4
Description
ADR14[9:2]
ADR15[9:2]
0
0
3
3
PS2
0
2
2
Analog Digital Converter - ADC
PS1
1
0
1
Access: User read/write
MM912F634
Bit 0
PS0
0
0
145
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