MM912F634DV1AE Freescale Semiconductor, MM912F634DV1AE Datasheet - Page 224
MM912F634DV1AE
Manufacturer Part Number
MM912F634DV1AE
Description
16-bit Microcontrollers - MCU DUAL LS/HS SWITCH W. LIN
Manufacturer
Freescale Semiconductor
Datasheet
1.MM912G634DV1AE.pdf
(338 pages)
Specifications of MM912F634DV1AE
Rohs
yes
Core
HCS12
Processor Series
MM912F634
Data Bus Width
16 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
32 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
4.5 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
15
Interface Type
SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
6
Number Of Timers
1
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
MM912F634DV1AE
Manufacturer:
FREESCALE
Quantity:
20 000
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Functional Description and Application Information
4.31.3.2.7.3
Table 284. Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst
in State3. The matches refer to the match channels of the comparator match control logic as depicted in
in
comparator enable bit in the associated DBGXCTL control register.
Table 285. DBGSCR3 Field Descriptions
Table 286. State3 — Sequencer Next State Selection
The priorities described in
(0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches.
Freescale Semiconductor
Address: 0x0027
Reset
Section 4.31.3.2.8.1, “Debug Comparator Control Register
SC[2:0]
SC[2:0]
W
R
000
001
010
011
100
101
110
111
Field
2–0
These bits select the targeted next state whilst in State3, based upon the match event.
0
0
7
Debug State Control Register 3 (DBGSCR3)
Table 311
0
0
6
dictate that in the case of simultaneous matches, the match on the lower channel number
5
0
0
Match2 to State2........ Match1 to Final State
Match1 to Final State....... Match2 to State1
Match2 to State2....... Match0 to Final State
Match0 to Final State.......Match1 to State1
Match1 to Final State
Match0 to Final State
0
0
4
(DBGXCTL)"”. Comparators must be enabled by setting the
Match0 to State1
Match1 to State2
Description
Description
0
0
3
SC2
S12S Debug (S12SDBGV1) Module
0
2
Figure 69
SC1
1
0
and described
MM912F634
SC0
0
0
224
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