S9S12G128F0CLFR Freescale Semiconductor, S9S12G128F0CLFR Datasheet - Page 673
S9S12G128F0CLFR
Manufacturer Part Number
S9S12G128F0CLFR
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12GN16F0CFT.pdf
(1292 pages)
Specifications of S9S12G128F0CLFR
Rohs
yes
Core
S12
Processor Series
S12G128
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0CLFR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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20.3.2.5
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Freescale Semiconductor
Module Base + 0x0002
BERRM[1:0]
RSEDGIE
BERRIE
BKDFE
BKDIE
Reset
Field
Field
2:1
7
1
0
0
W
R
BERRM1
Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag,
RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt
requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt
requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
0
0
1
SCI Alternative Control Register 2 (SCIACR2)
0
0
7
BERRM0
Figure 20-8. SCI Alternative Control Register 2 (SCIACR2)
0
1
0
= Unimplemented or Reserved
0
0
6
Bit error detect circuit is disabled
Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to
Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to
MC9S12G Family Reference Manual, Rev.1.23
Table 20-7. SCIACR1 Field Descriptions
Table 20-8. SCIACR2 Field Descriptions
Table 20-9. Bit Error Mode Coding
0
0
5
Figure
Figure
20-19)
20-19)
0
0
4
Description
Description
Function
0
0
3
Serial Communication Interface (S12SCIV5)
BERRM1
0
2
BERRM0
0
1
Table
BKDFE
20-9.
0
0
675
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