MK20DN512VLL10 Freescale Semiconductor, MK20DN512VLL10 Datasheet - Page 67

• Manufacturer Part Number: MK20DN512VLL10
• Description: ARM Microcontrollers - MCU Kinetis 512K
• Manufacturer: Freescale Semiconductor

Specifications of MK20DN512VLL10

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK20DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 2
• Interface Type: CAN, I2C, I2S, SPI, UART, USB
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Freescale Semiconductor, Inc.
LQFP
100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
PTE0
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTE3
PTE4/
LLWU_P2
PTE5
PTE6
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
VREF_OUT/
CMP1_IN5/
Pin Name
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
DISABLED
DISABLED
DISABLED
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
VREF_OUT/
CMP1_IN5/
Default
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
VREF_OUT/
CMP1_IN5/
ALT0
K20 Sub-Family Data Sheet, Rev. 2, 12/2012.
PTE0
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTE3
PTE4/
LLWU_P2
PTE5
PTE6
ALT1
SPI1_PCS1
SPI1_SOUT
SPI1_SCK
SPI1_SIN
SPI1_PCS0
SPI1_PCS2
SPI1_PCS3
ALT2
UART1_TX
UART1_RX
UART1_CTS_b SDHC0_DCLK
UART1_RTS_b SDHC0_CMD
UART3_TX
UART3_RX
UART3_CTS_b I2S0_MCLK
ALT3
SDHC0_D1
SDHC0_D0
SDHC0_D3
SDHC0_D2
ALT4
ALT5
I2C1_SDA
I2C1_SCL
ALT6
RTC_CLKOUT
SPI1_SIN
SPI1_SOUT
USB_SOF_
OUT
ALT7
EzPort
Pinout
67