MK21DN512VMC5 Freescale Semiconductor, MK21DN512VMC5 Datasheet - Page 22
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MK21DN512VMC5
Manufacturer Part Number
MK21DN512VMC5
Description
ARM Microcontrollers - MCU ARM+512Kb+USB+DryIce
Manufacturer
Freescale Semiconductor
Datasheet
1.MK21DN512VMC5.pdf
(59 pages)
Specifications of MK21DN512VMC5
Core
ARM Cortex M4
Processor Series
MK21DN512
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
MAPBGA-121
Mounting Style
SMD/SMT
A/d Bit Size
16 bit
Interface Type
Serial
Length
8 mm
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Timers
2
On-chip Dac
Yes
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.71 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MK21DN512VMC5
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MK21DN512VMC5
Manufacturer:
FREESCALE
Quantity:
20 000
Peripheral operating requirements and behaviors
22
Symbol
Symbol
J12
J13
J14
J10
J11
J12
J13
J14
J1
J2
J3
J4
J5
J6
J7
J8
J9
TCLK (input)
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Operating voltage
TCLK frequency of operation
TCLK cycle period
TCLK clock pulse width
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Description
Description
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Table 12. JTAG limited voltage range electricals (continued)
K21 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Table 13. JTAG full voltage range electricals
Figure 4. Test clock input timing
J4
J3
J2
J4
J3
1.71
1/J1
12.5
Min.
Min.
100
100
1.4
50
25
20
—
—
—
—
—
—
8
0
0
0
0
8
8
Freescale Semiconductor, Inc.
Max.
Max.
22.1
22.1
3.6
17
10
20
40
25
25
—
—
—
—
—
—
—
—
—
—
—
—
3
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V