MK21DN512VMC5 Freescale Semiconductor, MK21DN512VMC5 Datasheet - Page 49
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MK21DN512VMC5
Manufacturer Part Number
MK21DN512VMC5
Description
ARM Microcontrollers - MCU ARM+512Kb+USB+DryIce
Manufacturer
Freescale Semiconductor
Datasheet
1.MK21DN512VMC5.pdf
(59 pages)
Specifications of MK21DN512VMC5
Core
ARM Cortex M4
Processor Series
MK21DN512
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
MAPBGA-121
Mounting Style
SMD/SMT
A/d Bit Size
16 bit
Interface Type
Serial
Length
8 mm
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Timers
2
On-chip Dac
Yes
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.71 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MK21DN512VMC5
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MK21DN512VMC5
Manufacturer:
FREESCALE
Quantity:
20 000
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Freescale Semiconductor, Inc.
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Num.
Num.
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid
Table 35. I2S/SAI master mode timing (continued)
S5
S7
K21 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Figure 20. I2S/SAI timing — master modes
Characteristic
Characteristic
S4
Table 36. I2S/SAI slave mode timing
S9
S9
S1
S3
S2
S10
S4
S2
1
S8
0
25
0
1.71
80
45%
10
2
—
0
10
2
—
S7
Peripheral operating requirements and behaviors
Min.
Min.
—
—
—
3.6
—
55%
—
—
29
—
—
—
21
Max.
Max.
ns
ns
ns
V
ns
MCLK period
ns
ns
ns
ns
ns
ns
ns
Unit
Unit
S10
S6
S8
49