MK20FN1M0VMD12 Freescale Semiconductor, MK20FN1M0VMD12 Datasheet - Page 30

• Manufacturer Part Number: MK20FN1M0VMD12
• Description: ARM Microcontrollers - MCU KINETIS 1MB USB
• Manufacturer: Freescale Semiconductor

Specifications of MK20FN1M0VMD12

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: K20
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 1 MB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-144
• Mounting Style: SMD/SMT

Peripheral operating requirements and behaviors
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
30
t
f
f
Symbol
fll_acquire
vcoclk_90
vcoclk_2x
t
J
J
J
f
f
pll_lock
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
vcoclk
acc_pll
pll_ref
cyc_pll
cyc_fll
I
I
I
I
pll
pll
pll
pll
dco_t
) over voltage and temperature should be considered.
FLL period jitter
FLL target frequency acquisition time
PLL reference frequency range
VCO output frequency
PLL output frequency
PLL quadrature output frequency
PLL0 operating current
PLL0 operating current
PLL1 operating current
PLL1 operating current
Lock detector detection time
PLL period jitter (RMS)
PLL accumulated jitter over 1µs (RMS)
Description
• f
• f
• VCO @ 180 MHz (f
• VCO @ 360 MHz (f
• VCO @ 180 MHz (f
• VCO @ 360 MHz (f
• f
• f
• f
• f
= 8 MHz, VDIV multiplier = 22)
= 8 MHz, VDIV multiplier = 45)
= 8 MHz, VDIV multiplier = 22)
= 8 MHz, VDIV multiplier = 45)
VCO
VCO
vco
vco
vco
vco
= 180 MHz
= 360 MHz
= 180 MHz
= 360 MHz
= 48 MHz
= 98 MHz
Table 15. MCG specifications (continued)
K20 Sub-Family Data Sheet, Rev. 4, 10/2012.
osc_hi_1
osc_hi_1
osc_hi_1
osc_hi_1
= 32 MHz, f
= 32 MHz, f
= 32 MHz, f
= 32 MHz, f
pll_ref
pll_ref
pll_ref
pll_ref
PLL0,1
Min.
180
90
90
—
—
—
—
—
—
—
—
—
—
—
—
8
Typ.
180
150
100
600
300
2.8
4.7
2.3
3.6
75
—
—
—
—
—
—
100 × 10
+ 1075(1/
f
Max.
pll_ref
360
180
180
16
—
—
—
—
—
—
—
—
—
—
1
Freescale Semiconductor, Inc.
)
-6
MHz
MHz
MHz
MHz
Unit
mA
mA
mA
mA
ms
ps
ps
ps
ps
ps
s
Notes
10
6
7
7
7
7
8
9