MK20FN1M0VMD12 Freescale Semiconductor, MK20FN1M0VMD12 Datasheet - Page 65

no-image

MK20FN1M0VMD12

Manufacturer Part Number
MK20FN1M0VMD12
Description
ARM Microcontrollers - MCU KINETIS 1MB USB
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK20FN1M0VMD12

Rohs
yes
Core
ARM Cortex M4
Processor Series
K20
Data Bus Width
32 bit
Maximum Clock Frequency
120 MHz
Program Memory Size
1 MB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
MAPBGA-144
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK20FN1M0VMD12
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
6.8.7 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Freescale Semiconductor, Inc.
range the maximum frequency of operation is reduced.
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 44. Master mode DSPI timing (full voltage range)
Figure 28. DSPI classic SPI timing — slave mode
Description
K20 Sub-Family Data Sheet, Rev. 4, 10/2012.
DS13
DS15
First data
First data
DS14
DS10
DS12
Data
Data
(t
(t
(t
BUS
BUS
SCK
4 x t
Peripheral operating requirements and behaviors
1.71
20.5
Min.
-4.5
/2) - 4
4
4
0
x 2) −
x 2) −
BUS
DS11
DS9
(t
Last data
Last data
SCK/2)
Max.
3.6
15
10
+ 4
DS16
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Notes
1
2
3
65

Related parts for MK20FN1M0VMD12