MPC8308VMADDA Freescale Semiconductor, MPC8308VMADDA Datasheet - Page 74

• Manufacturer Part Number: MPC8308VMADDA
• Description: Microprocessors - MPU E300 MP PbFr 266
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMADDA

• Rohs: yes
• Processor Series: MPC8308
• Core: e300
• Maximum Clock Frequency: 266 MHz
• Interface Type: I2C, JTAG, UART
• Operating Supply Voltage: 0.95 V to 1.05 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-473

Thermal
21.3
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). This table shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in this table should be considered as reserved.
22 Thermal
This section describes the thermal specifications of the device.
74
1
2
Note:
For any core_clk:csb_clk ratios, the core_clk must not exceed its maximum operating frequency of 400 MHz.
Core VCO frequency = core frequency  VCO divider. Note that VCO divider has to be set properly so that the
core VCO frequency is in the range of 400–800 MHz.
0–1
nn
11
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
RCWL[COREPLL]
Core PLL Configuration
nnnn
0000
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0011
0011
0011
Core VCO frequency = core frequency VCO divider. The VCO divider,
which is determined by RCWLR[COREPLL], must be set properly so that
the core VCO frequency is in the range of 400–800 MHz.
2–5
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
6
0
n
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
(PLL off, csb_clk clocks core directly)
Table 58. e300 Core PLL Configuration
core_clk: csb_clk Ratio
PLL bypassed
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
2.5:1
n/a
1:1
1:1
1:1
2:1
2:1
2:1
3:1
3:1
3:1
NOTE
1
(PLL off, csb_clk clocks core directly)
VCO Divider (VCOD)
PLL bypassed
n/a
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
Freescale Semiconductor
2