MPC8308-RDB Freescale Semiconductor, MPC8308-RDB Datasheet

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... Overview Figure 1 shows the major functional units within the MPC8308. The e300 core in the MPC8308, with its 16 Kbytes of instruction and 16 Kbytes of data cache, implements the Power Architecture user instruction set architecture and provides hardware and software debugging support. In addition, the MPC8308 offers a PCI Express ...

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... Electrical Characteristics an SPI controller. The high level of integration in the MPC8308 helps simplify board design and offers significant bandwidth and performance. Figure 1 shows a block diagram of the device. DUART I2C Interrupt Timers Controller GPIO, SPI PCI Enhanced Express Secure Digital Host Controller 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8308 ...

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... Table 2. Recommended Operating Conditions Characteristic SerDes internal digital power SerDes internal digital power SerDes I/O digital power SerDes analog power for PLL SerDes analog power for PLL SerDes I/O digital power MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol XCOREV DD XPADV DD SDAV ...

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... The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode here refers to NV and LV DD1 DDC 6 Minimum temperature is specified with T MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev DD1 Section 23.2, “PLL Power Supply Filtering,” by the filter. DD ,NV ...

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... C, JTAG, eSDHC, GPIO,SPI, USB eTSEC signals 1 Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR). For more information, see the MPC8308 PowerQUICC II Pro Processor Reference Manual . 2.1.4 Power Sequencing The device does not require the core supply voltage ( applied in any particular order ...

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... Typical power is based on best process, a voltage 25° C and an artificial smoker test Maximum power is estimated based on best process, a voltage of V temperature MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev I/O Voltage (GV >= 32 × t Figure 3. Power-Up Sequencing Example Table 4. MPC8308 Power Dissipation CSB Frequency (MHz) Typical ...

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... Input low voltage SYS_CLK_IN input current Table 7 provides the RTC clock input (RTC_PIT_CLOCK) DC electrical specifications for the device. Table 7. RTC_PIT_CLOCK DC Electrical Characteristics Parameter Input high voltage Input low voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor (1.8 V) (3.3 V) 250 MHz 0.302 — ...

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... RESET DC Electrical Characteristics Table 10 provides the DC electrical characteristics for the RESET pins. Table 10. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Table 8 Symbol Min f 24 SYS_CLK_IN t ...

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... SYS_CLK_IN. SYS_CLK_IN 2. POR configuration signals consists of CFG_RESET_SOURCE[0:3]. Table 12 provides the PLL lock times. Parameter/Condition System PLL lock time e300 core PLL lock time MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol Condition Min 8.0 mA ...

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... Output leakage is measured with all outputs disabled Table 14 provides the DDR2 capacitance when Table 14. DDR2 SDRAM Capacitance for GV Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: 1. This parameter is sampled MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Symbol Min GV 1.7 DD 0.49 × REF ...

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... The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called t be determined by the following equation the absolute value of t CISKEW 3. Memory controller ODT value of 150 Ω is recommended MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor . REF Symbol Min I — ...

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... MCK[n] cycle time, MCK[n]/MCK[n] crossing ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS[n] output setup with respect to MCK MCS[n] output hold with respect to MCK MCK to MDQS Skew MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev MCK D0 D1 ...

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... The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t symbol conventions described in note 1. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor 1 ...

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... MCK[n] MDQS MDQS Figure 6 shows the DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x]/ MECC[x] Figure 6. DDR2 SDRAM Output Timing Diagram MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 5. Timing Diagram for t DDKHMH t MCK t ...

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... The middle of a start bit is detected as the 8 Subsequent bit values are sampled each 16 8 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8308 supports dual Ethernet controllers. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor = 50 Ω Figure 7 ...

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... Input low voltage V IL Input high current I IH Input low current I IL Note: 1. The symbol this case, represents the LV IN MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Section 8.3, “Ethernet Management Interface Table 21. MII DC Electrical Characteristics Conditions — –4 Min 4.0 mA ...

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... MTX the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Conditions — –1.0 mA ...

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... For example, the subscript of t MRX used with the appropriate letter: R (rise (fall). MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev MTX t ...

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... Data to clock output skew (at transmitter) Data to clock input skew (at receiver) 3 Clock cycle duration 4, 5 Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) Fall time (20%–80%) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t MRX t t MRXH MRXF Valid Data ...

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... Figure 11. RGMII AC Timing and Multiplexing Diagrams 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for MII MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev 2.5 V ± 5 ...

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... Table 27. MII Management AC Timing Specifications At recommended operating conditions with LV Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Conditions — –1 ...

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... IEEE 1588 Timer DC Specifications Table 28 provides the IEEE 1588 timer DC specifications. Table 28. GPIO DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev /LV is 3.3 V ± 0.3V DDA DDB 1 Symbol Min ...

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... High-level input voltage Low-level input voltage Input current = –100 μA High-level output voltage 100 μA Low-level output voltage Note: 1. The symbol this case, represents the NV IN MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol Condition V — ≤ V ≤ NVDD Symbol ...

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... Figure 13 and Figure 14 provide the AC test load and signals for the USB, respectively. Output USBDR_CLK Input Signals t USKHOV Output Signals MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Table 31. USB General Timing Parameters 1 Symbol t USCK t USIVKH t USIXKH ...

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... TXn) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor (or Differential Output Swing) OD – ...

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... SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK for PCI Express. The following sections describe the SerDes reference clock requirements and some application information. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev )/ which is the arithmetic mean of the two complimentary ...

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... AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. SD_REF_CLK SD_REF_CLK Figure 16. Receiver of SerDes Reference Clocks MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Table 1 50 Ω Input Amp 50 Ω ...

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... High-Speed Serial Interfaces (HSSI) 10.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8308 SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • Differential Mode — ...

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... LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Vmax < ...

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... MPC8308 SerDes reference clock receiver requirement provided in this document. Figure 20 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8308 SerDes reference clock input’s DC requirement. HCSL CLK Driver Chip CLK_Out 33 Ω ...

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... SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver’s common mode voltage is higher than the MPC8308’s SerDes reference clock input’s allowed range (100–400 mV), AC-coupled connection scheme must be used. It assumes the LVDS output driver features 50-Ω ...

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... R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8308’s SerDes reference clock’s differential input amplitude requirement (between 200 mV and 800 mV differential peak). For example, if the LVPECL output’ ...

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... At recommended operating conditions with XCOREVDD= 1.0V ± 5% Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK 50 Ω ...

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... The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based on application usage. For detailed information, see the following sections: • Section 11.2, “AC Requirements for PCI Express SerDes Clocks” MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Symbol Rise-Fall Matching 24) ...

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... REFCLK cycle time (for 125 MHz and 100 MHz) REF t REFCLK cycle-to-cycle jitter. Difference in the period REFCJ of any two adjacent REFCLK cycles. t Phase jitter. Deviation in edge location with respect to REFPJ mean edge location. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Ω 50 Ω Min 8 — ...

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... Minimum TX eye width T TX-EYE Maximum time between T TX-EYE-MEDIAN-t the jitter median and o- maximum deviation from MAX-JITTER the median MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Comments Min Each U is 400 ps ± 399.88 PETX 300 ppm. U does not PETX account for Spread Spectrum Clock dictated variations ...

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... Amount of voltage change V TX-RCV-DETECT allowed during receiver detection TX DC common mode V TX-DC-CM voltage TX short circuit current I TX-SHORT limit Minimum time spent in T TX-IDLE-MIN electrical idle MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Comments Min , — 0.125 V = — PEACPCMTX RMS(| |/2 - TXD+ TXD- V ...

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... Transmitter DC Z TX-DC impedance Lane-to-Lane output skew L TX-SKEW AC coupling capacitor C TX MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Comments Min After sending an Electrical — Idle ordered set, the Transmitter must meet all Electrical Idle Specifications within this time. This is considered a ...

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... UI recommended that the recovered calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Comments Min This random timeout helps ...

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... Table 35. Differential Receiver (RX) Input Specifications Parameter Symbol Unit interval UI Differential peak-to-peak V RX-DIFFp-p output voltage Minimum receiver eye T RX-EYE width MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev TX-DIFF [Transition Bit 800 mV TX-DIFFp-p-MIN [De-emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0 – 0.3 UI(J ...

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... Electrical idle detect V RX-IDLE-DET-DIF threshold Fp-p Unexpected Electrical Idle T RX-IDLE-DET-DIFF Enter Detect Threshold - Integration Time ENTERTIME MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Comments Min Jitter is defined as the — measurement variation of the crossing points ( PEDPPRX relation to a recovered TX UI. A recovered ...

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... The input receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in adequate combination of system simulations and the return loss measured looking into the RX package MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Comments Min Skew across all lanes on a — ...

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... The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor NOTE Figure 29) ...

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... Table 37. Local Bus General Timing Parameters Parameter Local bus cycle time Input setup to local bus clock (Note revisited) Input hold from local bus clock (Note revisited) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Symbol ...

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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 30 provides the AC test load for the local bus. Output MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor 1 Symbol t ...

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... In what follows, T1, T2, T3, and T4 are internal clock reference phase signals corresponding to LCCR[CLKDIV]. LCLK0 Input Signals: LD[0:15] Input Signal: LGTA t Output Signals: LBCTL//LOE/ Output Signals: LA[0:25] Figure 31. Local Bus Signals, Non-Special Signals Only MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev LBIVKH LBKHOV t LBKHOZ t LBKHOV t LBIXKH t LBIVKH ...

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... GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t ...

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... DC Electrical Characteristics Table 38 provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device, compatible with SDHC specifications. The eSDHC NV Table 38. eSDHC interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev LBKHOZ t LBKHOV t LBIVKH ...

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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2 Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications. 4 Average, for reference only. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol Condition 3 ...

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... SD CLK at the MPC8308 Pin SD CLK at the Card Pin Output Valid Time: t Output Hold Time: t Output from the MPC8308 Pins Input at the MPC8308 Pins MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev SFSCK VM = Midpoint Voltage ( (Clock Cycle) ...

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... Input setup times: SD_CMD, SD_DATx Input hold times: SD_CMD, SD_DATx Output delay time: SD_CLK to SD_CMD, SD_DATx valid Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid SD Card Input Setup SD Card Input Hold MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t (Clock Cycle) SFSCK t ...

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... Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications. Figure 37 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode Figure 37. eSDHC Clock Input Timing Diagram MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev 3.3 V ± 300 mV. 1 Symbol t ODLY t OH (first three letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... SD CLK at the MPC8308 Pin Driving SD CLK at the Card Pin Output from the SD Card Pins Input at the MPC8308 Pins MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t (Clock Cycle) SHSCK Driving Edge t CLK_DELAY SHSKHOV ...

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... JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Symbol Condition V — — ...

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... AC test load for TDO and the boundary-scan outputs. Output Figure 40. AC Test Load for the JTAG Interface Figure 41 provides the JTAG clock input timing diagram. JTAG External Clock Figure 41. JTAG Clock Input Timing Diagram MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Table 2). 2 Symbol t JTKLDX ...

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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 44. Test Access Port Timing Diagram MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev TRST VM = Midpoint Voltage (NV DD Figure 42. TRST Timing Diagram VM t JTDVKH ...

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... IN DD Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF For information on the digital filter used, see the MPC8308 PowerQUICC II Pro Processor Reference Manual . 2 15 Electrical Specifications Table 44 provides the AC timing parameters for the I ...

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... Figure 46 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Electrical Specifications (continued) Table 43). Parameter (first two letters of functional block)(signal)(state) (reference)(state) for outputs. For example symbolizes I C timing (I2) for the time that the data with respect to the start condition ( ...

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... Timers This section describes the DC and AC electrical specifications for the timers. 16.1 Timers DC Electrical Characteristics Table 45 provides the DC electrical characteristics for the MPC8308 timers pins, including TIN, TOUT, and TGATE. Table 45. Timers DC Electrical Characteristics Characteristic Output high voltage Output low voltage ...

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... GPIO 17 GPIO This section describes the DC and AC electrical specifications for the GPIO of MPC8308 17.1 GPIO DC Electrical Characteristics Table 47 provides the DC electrical characteristics for the GPIO. Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 17 ...

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... This section describes the DC and AC electrical specifications for the SPI of the device. 19.1 SPI DC Electrical Characteristics Table 51 provides the DC electrical characteristics for the MPC8308 SPI. Characteristic Input high voltage Input low voltage Input current MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Table 49. IPIC DC Electrical Characteristics Symbol Condition V — — ...

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... AC test load for the SPI. Output Figure 50 through Figure 51 represent the AC timing from generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Symbol Condition –8 ...

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... Figure 51. SPI AC Timing in Master Mode (Internal Clock) Diagram 20 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8308 is available in a moulded array process ball grid array (MAPBGA). For information on the MAPBGA, see “Package Parameters for the MPC8308 MAPBGA,” ...

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... Package and Pin Listings 20.2 Mechanical Dimensions of the MPC8308 MAPBGA Figure 52 shows the mechanical dimensions and bottom surface nomenclature of the MAPBGA package. Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG Notes: 1. All dimensions are in millimeters. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev ...

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... Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 20.3 Pinout Listings Table 53 provides the pin-out listing for the MPC8308, MAPBGA package. Signal MEMC_MDQ[0] MEMC_MDQ[1] MEMC_MDQ[2] MEMC_MDQ[3] ...

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... MEMC_MDQS[1] MEMC_MDQS[2] MEMC_MDQS[3] MEMC_MDQS[8] MEMC_MBA[0] MEMC_MBA[1] MEMC_MBA[2] MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MWE MEMC_MRAS MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Package Pin Number Pin Type M6 I/O M2 I/O M3 I/O L2 I/O L3 I/O AB2 ...

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... MEMC_MCK [1] MEMC_MCK [2] MEMC_MODT[0] MEMC_MODT[1] MEMC_MECC[0] MEMC_MECC[1] MEMC_MECC[2] MEMC_MECC[3] MEMC_MECC[4] MEMC_MECC[5] MEMC_MECC[6] MEMC_MECC[7] MV REF LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number Local Bus Controller Interface U18 ...

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... LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LCS[0] LCS[1] LCS[2] MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Package Pin Number Pin Type AC21 I/O AB20 I/O V16 I/O AA19 I/O AC17 I/O AC20 O Y16 ...

Page 69

... LCLK0 UART_SOUT1/MSRCID0/LSRCID0 UART_SIN1/MSRCID1/LSRCID1 UART_SOUT2/MSRCID2/LSRCID2 UART_SIN2/MSRCID3/LSRCID3 TXA TXA RXA RXA SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SD_PLL_TPA_ANA SDAVDD_0 SDAVSS_0 IIC_SDA1 IIC_SCL1 MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number Pin Type Y11 O AB11 O AC11 O U11 O Y10 O AA10 O AB10 O AC10 ...

Page 70

... TDO TMS TRST TEST_MODE HRESET PORESET SRESET SYS_CLK_IN RTC_PIT_CLOCK QUIESCE THERM0 TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RXD[3] MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Package Pin Number Pin Type D10 I/O C10 I/O Interrupts A17 F16 I/O B17 I/O A18 JTAG Y7 ...

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... SD_DAT[0]/GTM1_TOUT1/GPIO[20] SD_DAT[1]/GTM1_TOUT2/GPIO[21] SD_DAT[2]/GTM1_TIN2/GPIO[22] SD_DAT[3]/GTM1_TGATE2/GPIO[23] SPIMOSI/MSRCID4/LSRCID4 SPIMISO/MDVAL/LDVAL SPICLK SPISEL GPIO[0]/TSEC2_COL GPIO[1]/TSEC2_TX_ER GPIO[2]/TSEC2_GTX_CLK GPIO[3]/TSEC2_RX_CLK MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number Pin Type C21 C20 D20 C23 E23 F22 I/O F21 ...

Page 72

... USBDR_TXDRXD3 USBDR_TXDRXD4 USBDR_TXDRXD5 USBDR_TXDRXD6 USBDR_TXDRXD7 USBDR_PCTL0 USBDR_PCTL1 USBDR_STP TSEC_TMR_CLK/ GPIO[8] GTM1_TOUT3/ GPIO[9] GTM1_TOUT4/ GPIO[10] TSEC_TMR_TRIG1/ GPIO[11] TSEC_TMR_TRIG2/ GPIO[12] TSEC_TMR_GCLK MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Package Pin Number Pin Type J18 J20 H22 H21 H20 J21 J23 K22 K20 K18 ...

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... TSEC2_TMR_TX_ESFD/GPIO[2] TSEC1_TMR_RX_ESFD/GPIO[3] TSEC1_TMR_TX_ESFD/ GPIO[4] GTM1_TGATE3 GTM1_TIN4 GTM1_TGATE4/ GPIO[15] GTM1_TIN3 GPIO[5] GPIO[6] AV DD1 AV DD2 NC, No Connection V DD MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number L18 L21 L22 L23 M23 M22 M21 M18 M20 N23 N21 N20 N18 ...

Page 74

... DDG NV DDH NV DDJ NV DDP_K GV DD XPADVDD XPADVSS MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Package Pin Number Pin Type A2, A21, B1, B19, B23, I C4, C16, D6, D19, E3, F8, F15, F17, F23, G7, G8, G10, G15, G16, G17, G20, H2, H6, H7, H17, H23, J7, J9, J10, J11, J12, J13, J14, ...

Page 75

... The LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor enables the ECC by default. To disable the ECC an external strong pull up resistor or a buffer released to high impedance is needed. 8. This pin has weak internal pull-down that is always enabled MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number Pin Type ...

Page 76

... SerDes PHY clock • eSHDC clock (SD_CLK) For more information, see the SerDes chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual. All clock inputs can be supplied using an external canned oscillator, a clock generation chip, or some other source that provides a standard CMOS square wave input. ...

Page 77

... LBC clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK0:2). The LBC clock divider ratio is controlled by LCCR[CLKDIV]. For more information, see the Reset Clock Configuration chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual. ...

Page 78

... As described in Section 21, “Clocking,” configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Maximum Operating Frequency Table 56 Table 56. System PLL Ratio csb_clk: SYS_CLK_IN ...

Page 79

... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Table 57 shows the expected frequency values for the CSB frequency Table 57. CSB Frequency Options Input Clock Frequency (MHz) 25 2:1 4:1 5:1 125 shows the encodings for RCWL[COREPLL]. COREPLL values that are NOTE Table 58 ...

Page 80

... Table 59. Package Thermal Characteristics for MAPBGA Characteristic Junction to Ambient Natural Convection Junction to Ambient Natural Convection Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board Junction to Case Junction to Package Top MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev core_clk: csb_clk Ratio 2.5:1 3:1 3:1 3:1 Board Type ...

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... In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Board Type × ...

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... System Design Information This section provides electrical and thermal design recommendations for successful application of the device MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Ψ ) can be used to determine the junction temperature with a ...

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... This noise must be prevented from reaching other components in the MPC8308 system, and the MPC8308 itself requires a clean, tightly regulated source of power. Therefore recommended that the system designer place at least one decoupling capacitor at each V MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev ...

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... SW1 is closed (SW2 is open), and R NV /2. R then becomes the resistance of the pull-up devices other in value. Then MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev planes, to enable quick recharging of the smaller chip capacitors MDIO and HRESET) is trimmed until the voltage at the pad equals P )/2 ...

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... I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor NV ...

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... Part Numbers Fully Addressed by This Document Table 61 provides the Freescale part numbering nomenclature for the MPC8308 family. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the maximum processor core frequency, the part numbering scheme also includes the maximum effective DDR memory speed ...

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... Parts are marked as in the example shown in Figure 56. Freescale Part Marking for PBGA Devices Table 62 shows the SVR settings. Device MPC8308 Note: PVR = 8085_0020 for the device. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Figure 56. MPCnnnnCVMADDA core/platform MHZ ATWLYYWW ...

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... Table TSEC1_TMR_TX_ESFD replaced with TSEC2_TMR_TX_ESFD TSEC0_TMR_RX_ESFD replaced with TSEC1_TMR_RX_ESFD TSEC0_TMR_TX_ESFD replaced with TSEC1_TMR_TX_ESFD • In Table • In Table Rev 0 05/2010 Initial release MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Table 63. Document Revision History Substantive Change(s) to Note-7 in Table 1. DDJ 2, to Note-3 DDJ 4, Note-3, changed ambient temperature to junction temperature, T 18, changed from 3 ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Document Revision History 89 ...

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... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8308EC Rev. 2 02/2011 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...