MPC8308-RDB Freescale Semiconductor, MPC8308-RDB Datasheet - Page 79

• Manufacturer Part Number: MPC8308-RDB
• Description: BOARD REF DESIGN MPC8308
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MPUr

Specifications of MPC8308-RDB

• Contents: Board, Cables, Documentation, Power Supply, Software
• Ethernet Connection Type: Serial to Ethernet
• Data Rate: 10 Mbps, 100 Mbps, 1000 Mbps
• Memory Type: DDR2, SDRAM
• Interface Type: HSSI
• Operating Voltage: 1.5 V
• Operating Current: 5 uA
• Maximum Power Dissipation: 1000 mW
• Operating Temperature Range: - 55 C to + 125 C
• Product: Modules
• For Use With/related Products: MPC8308
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

coherent system bus clock (csb_clk).
for select csb_clk to SYS_CLK_IN ratios.
21.3
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
Freescale Semiconductor
0–1
nn
11
00
01
10
00
01
10
00
01
10
00
01
RCWL[COREPLL]
Core PLL Configuration
Table 58
0010
0100
0101
nnnn
0000
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
Core VCO frequency = core frequency × VCO divider. The VCO divider,
which is determined by RCWLR[COREPLL], must be set properly so that
the core VCO frequency is in the range of 400–800 MHz.
2–5
csb_clk :Input Clock Ratio
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
should be considered as reserved.
Table 58
6
0
n
0
0
0
1
1
1
0
0
0
1
1
SPMF
(PLL off, csb_clk clocks core directly)
shows the encodings for RCWL[COREPLL]. COREPLL values that are
2:1
4:1
5:1
Table 58. e300 Core PLL Configuration
core_clk: csb_clk Ratio
Table 57. CSB Frequency Options
Table 57
PLL bypassed
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
n/a
1:1
1:1
1:1
2:1
2:1
2:1
shows the expected frequency values for the CSB frequency
NOTE
125
1
25
Input Clock Frequency (MHz)
(PLL off, csb_clk clocks core directly)
33.33
VCO Divider (VCOD)
133
167
PLL bypassed
n/a
2
4
8
2
4
8
2
4
8
2
4
66.67
133
2
Clocking
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